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公开(公告)号：US11689316B2
公开(公告)日：2023-06-27
申请号：US17462055
申请日：2021-08-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sanjay Pennam , Vamsi Krishna Kandalla , Brahmendra Reddy Yatham , Shailesh Wardhen , Jaiganesh Balakrishnan , Jawaharlal Tangudu
CPC classification number: H04L1/0044 , H04B1/04 , H04L1/0042 , H04L1/0047 , H04L1/0061
Abstract: A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.
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公开(公告)号：US11422586B1
公开(公告)日：2022-08-23
申请号：US17488559
申请日：2021-09-29
Applicant: Texas Instruments Incorporated
Inventor： Aswath Vs , Sundarrajan Rangachari , Sarma Sundareswara Gunturi , Sanjay Pennam
Abstract: A system for generating secondary clock signals from a primary clock signal includes a dithered clock divider which has a first input adapted to receive the primary clock signal and a second input adapted to receive a random division ratio. The dithered clock divider provides a dithered clock signal. The system includes a multi-phase clock generator which has a first input adapted to receive the primary clock signal, a second input adapted to receive the dithered clock signal, and a third input adapted to receive a pseudo-random pattern. The multi-phase clock generator provides the secondary clock signals from multiple phases of the dithered clock signal. The system includes a pseudo-random pattern generator which provides the pseudo-random pattern.
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公开(公告)号：US10812091B2
公开(公告)日：2020-10-20
申请号：US16837537
申请日：2020-04-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sundarrajan Rangachari , Sriram Murali , Sanjay Pennam
Abstract: A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.
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Patent Agency Ranking
公开(公告)号：US20220271762A1
公开(公告)日：2022-08-25
申请号：US17488559
申请日：2021-09-29
Applicant: Texas Instruments Incorporated
Inventor： Aswath Vs , Sundarrajan Rangachari , Sarma Sundareswara Gunturi , Sanjay Pennam
Abstract: A system for generating secondary clock signals from a primary clock signal includes a dithered clock divider which has a first input adapted to receive the primary clock signal and a second input adapted to receive a random division ratio. The dithered clock divider provides a dithered clock signal. The system includes a multi-phase clock generator which has a first input adapted to receive the primary clock signal, a second input adapted to receive the dithered clock signal, and a third input adapted to receive a pseudo-random pattern. The multi-phase clock generator provides the secondary clock signals from multiple phases of the dithered clock signal. The system includes a pseuodo-random pattern generator which provides the pseudo-random pattern.
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公开(公告)号：US10651863B1
公开(公告)日：2020-05-12
申请号：US16269473
申请日：2019-02-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sundarrajan Rangachari , Sriram Murali , Sanjay Pennam
Abstract: A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.
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公开(公告)号：US20240364276A1
公开(公告)日：2024-10-31
申请号：US18648037
申请日：2024-04-26
Applicant: Texas Instruments Incorporated
Inventor： Chandrasekhar Sriram , Sarma Sundareswara Gunturi , Jawaharlal Tangudu , Harshit Moondra , Harsh Garg , Sanjay Pennam
CPC classification number: H03F1/3241 , H03F3/245 , H03F2200/451
Abstract: Methods, apparatus, systems, and articles of manufacture are described for dynamic digital pre-distortion correction. An example system includes programmable circuitry operable to execute computer readable instructions to at least: generate signal statistics based on an input signal; group the signal statistics into a first group of signal statistics or a second group of signal statistics based on time constants of the signal statistics; decimate the first group of signal statistics; generate a first predistortion term based on the decimated first group of signal statistics; generate a second predistortion term based on the second group of signal statistics; and generate an output predistortion terminal based on the first predistortion term and the second predistortion term.
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公开(公告)号：US20240297621A1
公开(公告)日：2024-09-05
申请号：US18592045
申请日：2024-02-29
Applicant: Texas Instruments Incorporated
Inventor： Jawaharlal Tangudu , Goutham Ramesh , Sarma Sundareswara Gunturi , Harsh Garg , Jaiganesh Balakrishnan , Mathews John , Sashidharan Venkatraman , Sanjay Pennam
CPC classification number: H03F1/3241 , H03F3/21 , H03F2201/3233
Abstract: An example method includes switching a first multiplexer circuit associated with first delay circuitry from (a) a first sub-lookup table (LUT) of a first LUT of digital pre-distortion (DPD) corrector circuitry to (b) a first corresponding sub-LUT of a second LUT of the DPD corrector circuitry, the first sub-LUT associated with the first delay circuitry, the second LUT storing updated values to compensate for non-linearity of power amplifier circuitry of a transmitter including the DPD corrector circuitry. The method includes, based on a value of a counter being equal to a difference between (1) a first delay of the first delay circuitry and (2) a second delay of second delay circuitry, switching a second multiplexer circuit associated with the second delay circuitry from (a) a second sub-LUT of the first LUT to (b) a second corresponding sub-LUT of the second LUT, the second sub-LUT associated with the second delay circuitry.
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公开(公告)号：US11139916B2
公开(公告)日：2021-10-05
申请号：US16936065
申请日：2020-07-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sanjay Pennam , Vamsi Krishna Kandalla , Brahmendra Reddy Yatham , Shailesh Wardhen , Jaiganesh Balakrishnan , Jawaharlal Tangudu
Abstract: A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.
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