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公开(公告)号：US11411387B2
公开(公告)日：2022-08-09
申请号：US16658311
申请日：2019-10-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mayank Jain , Preetam Tadeparthy , Rohit Narula , Shobhit Singhal
Abstract: An over/under voltage protection circuit includes a voltage input terminal, a digital-to analog converter, a comparator, and a control circuit. The comparator includes a first input coupled to an output of the digital-to-analog converter, and a second input coupled to the voltage input terminal. The control circuit includes an output coupled to an input of the digital-to-analog converter, and an input coupled to an output of the comparator. The control circuit is configured to set the digital-to-analog converter to generate an overvoltage fault threshold responsive to the output of the comparator indicating that voltage of a signal at the voltage input terminal exceeds a threshold currently generated by the digital-to-analog converter.
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公开(公告)号：US20230076376A1
公开(公告)日：2023-03-09
申请号：US17470528
申请日：2021-09-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Robin O. Hoel , Eric Peeters , Prithvi Shankar Yeyyadi Anantha , Aniruddha Periyapatna Nagendra , Shobhit Singhal , Ruchi Shankar , Prachi Mishra
Abstract: A microcontroller is provided and comprises a central repository, a processing device, and a firewall. Rule repository memory in the central repository stores one or more access rules defining an access permission of a software context to one or more target resources of the microcontroller. The firewall receives a bus transaction initiated based on an instruction and determines whether any access rule stored in memory of the firewall defines the access permission of the software context to a destination resource. If no access rule stored in the firewall memory defines the access permission, the firewall communicates a miss query condition to the central repository. The central repository searches the rule repository memory for an access rule defining the access permission of the software context to the destination resource, and if a related access rule is found, the related access rule is stored in the firewall memory.
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公开(公告)号：US11899954B2
公开(公告)日：2024-02-13
申请号：US17590884
申请日：2022-02-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shobhit Singhal , Ruchi Shankar , Sverre Brubaek , Praveen Kumar N
IPC: G06F3/06
CPC classification number: G06F3/0635 , G06F3/0619 , G06F3/0673
Abstract: A memory system includes a main memory, an auxiliary memory, a redundancy circuit, an extension control terminal, and a multiplexer. The main memory has a line width, and includes a write data input. The auxiliary memory has the same line width as the main memory, and includes a write data input. The redundancy circuit includes and input and an output. The input is coupled to the write data input of the main memory. The multiplexer includes a first input, a second input, a control input, and an output. The first input is coupled to the write data input of the main memory. The second input is coupled to the output of the redundancy circuit. The control input is coupled to the extension control terminal. The output of the multiplexer is coupled to the write data input of the auxiliary memory.
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公开(公告)号：US20230197143A1
公开(公告)日：2023-06-22
申请号：US17558176
申请日：2021-12-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ruchi Shankar , Shobhit Singhal , Sverre Brubæk , Praveen Kumar Narayanan
IPC: G11C11/412 , G11C11/419
CPC classification number: G11C11/412 , G11C11/419 , G11C11/418
Abstract: A static random-access memory (SRAM) includes a SRAM cell module, comprising a plurality of SRAM cell partitions, and an initialization register, containing data configured to control initialization of at least some of the plurality of partitions during an initialization phase. The SRAM also includes a control module coupled with the SRAM cell module and the initialization register, configured to read the initialization register during the initialization phase, and to selectively initialize a portion of the plurality of SRAM cell partitions, based at least in part on the data contained within the initialization register.
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公开(公告)号：US20220159128A1
公开(公告)日：2022-05-19
申请号：US17592643
申请日：2022-02-04
Applicant: Texas Instruments Incorporated
Inventor： Shobhit Singhal , Vikas Lakhanpal , Preetam Tadeparthy
Abstract: Aspects of the disclosure provide for a circuit, in some examples, including a storage element, a co-processor, and a telemetry sequencer coupled to the storage element and the co-processor. The telemetry sequencer is configured to implement a digital state machine to receive configuration information indicating a type of telemetry data for generation, retrieve operations and operands, where the operations and the operands define a sequential series of actions for execution to generate the telemetry data, drive the co-processor with the operations and the operands by passing some of the operations and some of the operands to the co-processor for processing by the co-processor, receive, from the co-processor, and store an intermediate output of the series of actions as the telemetry data in a first format, and receive, from the co-processor, and store a final output of the series of actions as the telemetry data in a second format.
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Patent Agency Ranking
公开(公告)号：US12046275B2
公开(公告)日：2024-07-23
申请号：US17558176
申请日：2021-12-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ruchi Shankar , Shobhit Singhal , Sverre Brubæk , Praveen Kumar Narayanan
IPC: G06F9/445 , G11C11/412 , G11C11/419 , G11C11/418
CPC classification number: G11C11/412 , G11C11/419 , G11C11/418
Abstract: A static random-access memory (SRAM) includes a SRAM cell module, comprising a plurality of SRAM cell partitions, and an initialization register, containing data configured to control initialization of at least some of the plurality of partitions during an initialization phase. The SRAM also includes a control module coupled with the SRAM cell module and the initialization register, configured to read the initialization register during the initialization phase, and to selectively initialize a portion of the plurality of SRAM cell partitions, based at least in part on the data contained within the initialization register.
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公开(公告)号：US11700336B2
公开(公告)日：2023-07-11
申请号：US17592643
申请日：2022-02-04
Applicant: Texas Instruments Incorporated
Inventor： Shobhit Singhal , Vikas Lakhanpal , Preetam Tadeparthy
CPC classification number: H04M11/002 , A61N1/37252 , G01R19/12 , G06F9/3877
Abstract: Aspects of the disclosure provide for a circuit, in some examples, including a storage element, a co-processor, and a telemetry sequencer coupled to the storage element and the co-processor. The telemetry sequencer is configured to implement a digital state machine to receive configuration information indicating a type of telemetry data for generation, retrieve operations and operands, where the operations and the operands define a sequential series of actions for execution to generate the telemetry data, drive the co-processor with the operations and the operands by passing some of the operations and some of the operands to the co-processor for processing by the co-processor, receive, from the co-processor, and store an intermediate output of the series of actions as the telemetry data in a first format, and receive, from the co-processor, and store a final output of the series of actions as the telemetry data in a second format.
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公开(公告)号：US08942333B2
公开(公告)日：2015-01-27
申请号：US13674154
申请日：2012-11-12
Applicant: Texas Instruments Incorporated
Inventor： Arvind Kumar , Shobhit Singhal , Vikas Lakhanpal , Kalpesh Amrutlal Shah
CPC classification number: H04L7/0037 , G01R25/04 , H03L7/0814 , H04L7/0012 , H04L7/0045
Abstract: Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY interface in a system on a chip system. A first circuit samples a phase of a first clock used by the first circuitry system, and then a delay circuit selectively delays a second clock used by the second circuitry system and sets a delayed timing of the second clock. To economize resources and reduce chip area, a logic circuit receives the sampled phase of the first clock, determines which delayed timing matches timing of the sampled phase, and sets the delay circuit to a fixed delayed timing corresponding to the delayed timing that matches the sampled phase. Thus, phase alignment of the two clocks is achieved with fewer resources.
Abstract translation: 用于相位对准由相应的第一和第二电路系统使用的至少两个时钟的装置和方法，例如芯片系统上的系统中的存储器控制器和DDR PHY接口。 第一电路对第一电路系统使用的第一时钟的相位进行采样，然后延迟电路选择性地延迟第二电路系统使用的第二时钟并设置第二时钟的延迟定时。 为了节省资源并减少芯片面积，逻辑电路接收第一时钟的采样相位，确定哪个延迟定时与采样相位的时序相匹配，并将延迟电路设置为对应于与采样相关的延迟定时相对应的固定延迟定时 相。 因此，通过较少的资源实现两个时钟的相位对准。
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公开(公告)号：US20140133613A1
公开(公告)日：2014-05-15
申请号：US13674154
申请日：2012-11-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Arvind Kumar , Shobhit Singhal , Vikas Lakhanpal , Kalpesh Amrutlal Shah
IPC: H04L7/02
CPC classification number: H04L7/0037 , G01R25/04 , H03L7/0814 , H04L7/0012 , H04L7/0045
Abstract: Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY interface in a system on a chip system. A first circuit samples a phase of a first clock used by the first circuitry system, and then a delay circuit selectively delays a second clock used by the second circuitry system and sets a delayed timing of the second clock. To economize resources and reduce chip area, a logic circuit receives the sampled phase of the first clock, determines which delayed timing matches timing of the sampled phase, and sets the delay circuit to a fixed delayed timing corresponding to the delayed timing that matches the sampled phase. Thus, phase alignment of the two clocks is achieved with fewer resources.
Abstract translation: 用于相位对准由相应的第一和第二电路系统使用的至少两个时钟的装置和方法，例如芯片系统上的系统中的存储器控制器和DDR PHY接口。 第一电路对第一电路系统使用的第一时钟的相位进行采样，然后延迟电路选择性地延迟第二电路系统使用的第二时钟并设置第二时钟的延迟定时。 为了节省资源并减少芯片面积，逻辑电路接收第一时钟的采样相位，确定哪个延迟定时与采样相位的时序相匹配，并将延迟电路设置为对应于与采样相关的延迟定时相对应的固定延迟定时 相。 因此，通过较少的资源实现两个时钟的相位对准。
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公开(公告)号：US12137081B2
公开(公告)日：2024-11-05
申请号：US17470528
申请日：2021-09-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Robin O. Hoel , Eric Peeters , Prithvi Shankar Yeyyadi Anantha , Aniruddha Periyapatna Nagendra , Shobhit Singhal , Ruchi Shankar , Prachi Mishra
Abstract: A microcontroller is provided and comprises a central repository, a processing device, and a firewall. Rule repository memory in the central repository stores one or more access rules defining an access permission of a software context to one or more target resources of the microcontroller. The firewall receives a bus transaction initiated based on an instruction and determines whether any access rule stored in memory of the firewall defines the access permission of the software context to a destination resource. If no access rule stored in the firewall memory defines the access permission, the firewall communicates a miss query condition to the central repository. The central repository searches the rule repository memory for an access rule defining the access permission of the software context to the destination resource, and if a related access rule is found, the related access rule is stored in the firewall memory.
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