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公开(公告)号：US20230195565A1
公开(公告)日：2023-06-22
申请号：US17557747
申请日：2021-12-21
Applicant: Texas Instruments Incorporated
Inventor： Ruchi Shankar , Tejas Dhanajirao Salunkhe , Trevor Charles Jones
IPC: G06F11/10 , G06F11/07 , G06F12/0811
CPC classification number: G06F11/1064 , G06F11/0772 , G06F11/1048 , G06F12/0811
Abstract: In described examples, a memory system is accessed by reading a data line and error detection bits for the data line from a first memory. The data line and the error detection bits from the first memory are decoded to determine if an error is present in the data line from the first memory. A copy of the data line and the error detection bits are stored in a second memory. The copy of the data line and error detection bits are read from the second memory. The copy of the data line and error detection bits are decoded to determine if an error is present in the copy of the data line from the second memory.
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公开(公告)号：US20240071561A1
公开(公告)日：2024-02-29
申请号：US17823599
申请日：2022-08-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Robin O. Hoel , Praveen Kumar Narayanan , Ruchi Shankar
IPC: G11C29/00 , G11C11/418
CPC classification number: G11C29/883 , G11C11/418
Abstract: An electronic system includes a repair MMR coupled with a first SRAM module within a plurality of SRAM modules coupled with each other in a daisy-chain configuration on a repair interface, and coupled with a last SRAM module within the plurality of SRAM modules via the repair interface. The electronic system also includes storage memory configured to store repair data for the plurality of SRAM modules and repair instructions, and processing circuitry. The processing circuitry is configured to, during boot up of the electronic system, read repair data for one or more of the plurality of SRAM modules from the storage memory, create serialized repair data for one or more the plurality of SRAM modules based on the repair instructions and the repair data, and to sequentially transmit the serialized repair data to the MMR.
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公开(公告)号：US20230076376A1
公开(公告)日：2023-03-09
申请号：US17470528
申请日：2021-09-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Robin O. Hoel , Eric Peeters , Prithvi Shankar Yeyyadi Anantha , Aniruddha Periyapatna Nagendra , Shobhit Singhal , Ruchi Shankar , Prachi Mishra
Abstract: A microcontroller is provided and comprises a central repository, a processing device, and a firewall. Rule repository memory in the central repository stores one or more access rules defining an access permission of a software context to one or more target resources of the microcontroller. The firewall receives a bus transaction initiated based on an instruction and determines whether any access rule stored in memory of the firewall defines the access permission of the software context to a destination resource. If no access rule stored in the firewall memory defines the access permission, the firewall communicates a miss query condition to the central repository. The central repository searches the rule repository memory for an access rule defining the access permission of the software context to the destination resource, and if a related access rule is found, the related access rule is stored in the firewall memory.
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公开(公告)号：US10545908B2
公开(公告)日：2020-01-28
申请号：US15055836
申请日：2016-02-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Bhargavi Nisarga , Ruchi Shankar
Abstract: Methods, apparatus, systems, and articles of manufacture to enable status change detection in a low power mode of a microcontroller unit are disclosed herein. An example integrated circuit (IC) includes a controller to determine that the IC is to enter a low power mode. The example IC includes a universal serial bus (USB) physical layer integrated circuit including a transceiver and a detector circuit. The transceiver is disabled while in the low power mode. The detector circuit is enabled while in the low power mode. The detector circuit is to determine whether a pinout of a USB receptacle is shorted to ground. The example IC includes a power control module (PCM) to disable the controller when entering the low power mode. Upon receipt of an indication that the ID pinout of the USB receptacle is shorted to the ground, the PCM initiates a boot sequence.
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公开(公告)号：US12137081B2
公开(公告)日：2024-11-05
申请号：US17470528
申请日：2021-09-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Robin O. Hoel , Eric Peeters , Prithvi Shankar Yeyyadi Anantha , Aniruddha Periyapatna Nagendra , Shobhit Singhal , Ruchi Shankar , Prachi Mishra
Abstract: A microcontroller is provided and comprises a central repository, a processing device, and a firewall. Rule repository memory in the central repository stores one or more access rules defining an access permission of a software context to one or more target resources of the microcontroller. The firewall receives a bus transaction initiated based on an instruction and determines whether any access rule stored in memory of the firewall defines the access permission of the software context to a destination resource. If no access rule stored in the firewall memory defines the access permission, the firewall communicates a miss query condition to the central repository. The central repository searches the rule repository memory for an access rule defining the access permission of the software context to the destination resource, and if a related access rule is found, the related access rule is stored in the firewall memory.
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Patent Agency Ranking
公开(公告)号：US20210034089A1
公开(公告)日：2021-02-04
申请号：US17064480
申请日：2020-10-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ruchi Shankar , Somshubhra Paul , Gaurang Helekar
Abstract: A system includes a voltage regulator having an output voltage and a power management system, coupled to the voltage regulator. The power management system operable to determine whether the output voltage is within an active range, set the active range to a first range during a first time, or during a first mode, and set the active range to a second range for a second time, or during a second mode.
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7.发明申请公开(公告)号：US20170249166A1
公开(公告)日：2017-08-31
申请号：US15055836
申请日：2016-02-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Bhargavi Nisarga , Ruchi Shankar
CPC classification number: G06F13/4282 , G06F1/325 , G06F1/3253 , G06F13/4068 , Y02D10/14 , Y02D10/151
Abstract: Methods, apparatus, systems, and articles of manufacture to enable status change detection in a low power mode of a microcontroller unit are disclosed herein. An example integrated circuit (IC) includes a controller to determine that the IC is to enter a low power mode. The example IC includes a universal serial bus (USB) physical layer integrated circuit including a transceiver and a detector circuit. The transceiver is disabled while in the low power mode. The detector circuit is enabled while in the low power mode. The detector circuit is to determine whether a pinout of a USB receptacle is shorted to ground. The example IC includes a power control module (PCM) to disable the controller when entering the low power mode. Upon receipt of an indication that the ID pinout of the USB receptacle is shorted to the ground, the PCM initiates a boot sequence.
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公开(公告)号：US20250076945A1
公开(公告)日：2025-03-06
申请号：US18498757
申请日：2023-10-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ruchi Shankar , Robin O. Hoel , Patrick Seem , Oddgeir Fikstvedt , Jan-Tore Marienborg
IPC: G06F1/26 , G06F1/3203 , H03K3/356 , H03K19/0185
Abstract: Embodiments disclosed herein relate to split rail architecture for power supplies in a system, and more particularly, to providing isolation and control of a power supply. In an example, an integrated circuit device is provided that includes a device voltage supply, an input/output (I/O) voltage supply coupled to the device voltage supply, and a level shifter circuit coupled to the I/O voltage supply. The level shifter circuit includes a pair of cross-coupled p-type metal-oxide semiconductor field effect transistors (PMOS transistors), a pair of n-type transistors (NMOS transistors) coupled between the pair of cross-coupled PMOS transistors and a ground connection, and an inverter circuit coupled to the device voltage supply and the level shifter circuit. The level shifter circuit further includes a capacitor coupled to the pair of cross-coupled PMOS transistors and the ground connection and is in parallel with respect to a first one of the pair of NMOS transistors.
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公开(公告)号：US11899954B2
公开(公告)日：2024-02-13
申请号：US17590884
申请日：2022-02-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shobhit Singhal , Ruchi Shankar , Sverre Brubaek , Praveen Kumar N
IPC: G06F3/06
CPC classification number: G06F3/0635 , G06F3/0619 , G06F3/0673
Abstract: A memory system includes a main memory, an auxiliary memory, a redundancy circuit, an extension control terminal, and a multiplexer. The main memory has a line width, and includes a write data input. The auxiliary memory has the same line width as the main memory, and includes a write data input. The redundancy circuit includes and input and an output. The input is coupled to the write data input of the main memory. The multiplexer includes a first input, a second input, a control input, and an output. The first input is coupled to the write data input of the main memory. The second input is coupled to the output of the redundancy circuit. The control input is coupled to the extension control terminal. The output of the multiplexer is coupled to the write data input of the auxiliary memory.
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公开(公告)号：US20230197143A1
公开(公告)日：2023-06-22
申请号：US17558176
申请日：2021-12-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ruchi Shankar , Shobhit Singhal , Sverre Brubæk , Praveen Kumar Narayanan
IPC: G11C11/412 , G11C11/419
CPC classification number: G11C11/412 , G11C11/419 , G11C11/418
Abstract: A static random-access memory (SRAM) includes a SRAM cell module, comprising a plurality of SRAM cell partitions, and an initialization register, containing data configured to control initialization of at least some of the plurality of partitions during an initialization phase. The SRAM also includes a control module coupled with the SRAM cell module and the initialization register, configured to read the initialization register during the initialization phase, and to selectively initialize a portion of the plurality of SRAM cell partitions, based at least in part on the data contained within the initialization register.
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