公开(公告)号：US20200020620A1

公开(公告)日：2020-01-16

申请号：US16032958

申请日：2018-07-11

Applicant: Texas Instruments Incorporated

Inventor： Siva Prakash Gurrum ,  Manu J. Prakuzhy ,  Saumya Gandhi

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/56

Abstract: In a described example, a packaged device includes a substrate having a device mounting surface including a first layer of conductive material having a first thickness less than a substrate thickness, the substrate having a second layer of the conductive material having a second thickness less than the substrate thickness. A first semiconductor device is mounted to a first area of the device mounting surface; and a second semiconductor device is mounted to a second area on the device mounting surface and spaced from the first semiconductor device. At least two connectors are formed of the first layer of the substrate having first ends coupled to one of first bond pads on the first semiconductor device and the at least two connectors having second ends coupled to one of second bond pads on the second semiconductor device.

公开(公告)号：US10446414B2

公开(公告)日：2019-10-15

申请号：US15853345

申请日：2017-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amit Sureshkumar Nangia ,  Siva Prakash Gurrum ,  Janakiraman Seetharaman

IPC: H01L21/56 ,  H01L23/29 ,  H01L23/495 ,  C08G59/18 ,  H01L23/64 ,  H01L23/522 ,  H01L23/00 ,  H01L23/50

Abstract: A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.

公开(公告)号：US20180233422A1

公开(公告)日：2018-08-16

申请号：US15896860

申请日：2018-02-14

Applicant: Texas Instruments Incorporated

Inventor： Siva Prakash Gurrum ,  Amit Sureshkumar Nangia

IPC: H01L23/16 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/16 ,  H01L23/295 ,  H01L23/3135 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/562 ,  H01L24/03 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/48247 ,  H01L2224/49175

Abstract: A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.

公开(公告)号：US12159808B2

公开(公告)日：2024-12-03

申请号：US18075288

申请日：2022-12-05

Applicant: Texas Instruments Incorporated

Inventor： Hung-Yun Lin ,  Siva Prakash Gurrum

IPC: H01L21/66 ,  G01R1/067 ,  G01R31/52 ,  H01L23/00 ,  H01L23/495 ,  H01L23/522 ,  H01L23/528

Abstract: An integrated circuit (IC) includes semiconductor substrate with a metal stack including a lower, upper and a top metal layer that includes bond pads and a detection bond pad (DBP). A wirebond damage detector (WDD) includes the DBP over a first and second connected structure. The first and second connected structures both include spaced apart top segments of the upper metal layer coupled to spaced apart bottom segments of the lower metal layer. The DBP is coupled to one end of the first connected structure, and ≥1 metal trace is coupled to another end extending beyond the DBP to a first test pad. The second connected structure includes metal traces coupled to respective ends each extending beyond the DBP to a second test pad and to a third test pad.

公开(公告)号：US20230100709A1

公开(公告)日：2023-03-30

申请号：US18075288

申请日：2022-12-05

Applicant: Texas Instruments Incorporated

Inventor： Hung-Yun Lin ,  Siva Prakash Gurrum

IPC: H01L21/66 ,  H01L23/522 ,  H01L23/528 ,  H01L23/495 ,  H01L23/00 ,  G01R31/52 ,  G01R1/067

Abstract: An integrated circuit (IC) includes semiconductor substrate with a metal stack including a lower, upper and a top metal layer that includes bond pads and a detection bond pad (DBP). A wirebond damage detector (WDD) includes the DBP over a first and second connected structure. The first and second connected structures both include spaced apart top segments of the upper metal layer coupled to spaced apart bottom segments of the lower metal layer. The DBP is coupled to one end of the first connected structure, and >1 metal trace is coupled to another end extending beyond the DBP to a first test pad. The second connected structure includes metal traces coupled to respective ends each extending beyond the DBP to a second test pad and to a third test pad.

公开(公告)号：US20220336304A1

公开(公告)日：2022-10-20

申请号：US17810568

申请日：2022-07-01

Applicant: Texas Instruments Incorporated

Inventor： Amit Sureshkumar Nangia ,  Sreenivasan Kalyani Koduri ,  Siva Prakash Gurrum ,  Christopher Daniel Manack

IPC: H01L23/16 ,  H01L23/00

Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.

公开(公告)号：US20210287950A1

公开(公告)日：2021-09-16

申请号：US16815130

申请日：2020-03-11

Applicant: Texas Instruments Incorporated

Inventor： Hung-Yun Lin ,  Siva Prakash Gurrum

IPC: H01L21/66 ,  H01L23/522 ,  H01L23/528 ,  H01L23/495 ,  H01L23/00 ,  G01R31/52 ,  G01R1/067

Abstract: An integrated circuit (IC) includes semiconductor substrate with a metal stack including a lower, upper and a top metal layer that includes bond pads and a detection bond pad (DBP). A wirebond damage detector (WDD) includes the DBP over a first and second connected structure. The first and second connected structures both include spaced apart top segments of the upper metal layer coupled to spaced apart bottom segments of the lower metal layer. The DBP is coupled to one end of the first connected structure, and ≥1 metal trace is coupled to another end extending beyond the DBP to a first test pad. The second connected structure includes metal traces coupled to respective ends each extending beyond the DBP to a second test pad and to a third test pad.

公开(公告)号：US20200043753A1

公开(公告)日：2020-02-06

申请号：US16653536

申请日：2019-10-15

Applicant: Texas Instruments Incorporated

Inventor： Amit Sureshkumar Nangia ,  Siva Prakash Gurrum ,  Janakiraman Seetharaman

IPC: H01L21/56 ,  H01L23/29 ,  H01L23/495 ,  C08G59/18 ,  H01L23/64 ,  H01L23/522 ,  H01L23/00 ,  H01L23/50 ,  H01L23/31

Abstract: A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.

公开(公告)号：US11538742B2

公开(公告)日：2022-12-27

申请号：US16848774

申请日：2020-04-14

Applicant: Texas Instruments Incorporated

Inventor： Siva Prakash Gurrum ,  Manu J. Prakuzhy ,  Saumya Gandhi

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/00 ,  H01L21/56

Abstract: In a described example, a packaged device includes a substrate having a device mounting surface including a first layer of conductive material having a first thickness less than a substrate thickness, the substrate having a second layer of the conductive material having a second thickness less than the substrate thickness. A first semiconductor device is mounted to a first area of the device mounting surface; and a second semiconductor device is mounted to a second area on the device mounting surface and spaced from the first semiconductor device. At least two connectors are formed of the first layer of the substrate having first ends coupled to one of first bond pads on the first semiconductor device and the at least two connectors having second ends coupled to one of second bond pads on the second semiconductor device.

公开(公告)号：US11121049B2

公开(公告)日：2021-09-14

申请号：US16249756

申请日：2019-01-16

Applicant: Texas Instruments Incorporated

Inventor： Siva Prakash Gurrum ,  Amit Sureshkumar Nangia

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/16 ,  H01L23/29 ,  H01L23/31

Abstract: A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.