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公开(公告)号：US20230102688A1
公开(公告)日：2023-03-30
申请号：US17487318
申请日：2021-09-28
摘要： In a described example, an apparatus includes: a semiconductor die with a component on a device side surface; a die seal surrounding the component on the device side surface; a package substrate having bond pads on a die side surface; a package substrate seal formed on the die side surface of the package substrate corresponding to the die seal on the semiconductor die; the semiconductor die flip chip mounted on the bond pads of the package substrate with solder joints connecting post connects on the semiconductor die to the bond pads of the package substrate; a mold compound seal formed by the die seal and the package substrate seal; and mold compound covering a portion of the semiconductor die, a portion of the die side of the package substrate, and contacting the mold compound seal, the mold compound spaced from the component.
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公开(公告)号：US20210296196A1
公开(公告)日：2021-09-23
申请号：US16826047
申请日：2020-03-20
IPC分类号： H01L23/31 , H01L23/498 , H01L23/00 , H01L21/56
摘要： A described example includes: a semiconductor device die with an active surface; the semiconductor device die mounted on a package substrate with substrate leads and the semiconductor device die electrically coupled to the substrate leads; at least a first rigid low expansion material (RLEM) covering a portion of the semiconductor device die; and the first RLEM, the semiconductor device die, and a portion of the substrate leads covered with mold compound and forming a packaged semiconductor device die.
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公开(公告)号：US10446414B2
公开(公告)日：2019-10-15
申请号：US15853345
申请日：2017-12-22
IPC分类号： H01L21/56 , H01L23/29 , H01L23/495 , C08G59/18 , H01L23/64 , H01L23/522 , H01L23/00 , H01L23/50
摘要： A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.
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公开(公告)号：US20180233422A1
公开(公告)日：2018-08-16
申请号：US15896860
申请日：2018-02-14
IPC分类号： H01L23/16 , H01L23/495 , H01L23/00
CPC分类号： H01L23/16 , H01L23/295 , H01L23/3135 , H01L23/49503 , H01L23/4952 , H01L23/49541 , H01L23/562 , H01L24/03 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/48247 , H01L2224/49175
摘要： A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.
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公开(公告)号：US20220336304A1
公开(公告)日：2022-10-20
申请号：US17810568
申请日：2022-07-01
发明人： Amit Sureshkumar Nangia , Sreenivasan Kalyani Koduri , Siva Prakash Gurrum , Christopher Daniel Manack
摘要： An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.
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公开(公告)号：US20220246489A1
公开(公告)日：2022-08-04
申请号：US17723439
申请日：2022-04-18
IPC分类号： H01L23/31 , H01L23/498 , H01L23/00 , H01L21/56
摘要： A described example includes: a semiconductor device die with an active surface; the semiconductor device die mounted on a package substrate with substrate leads and the semiconductor device die electrically coupled to the substrate leads; at least a first rigid low expansion material (RLEM) covering a portion of the semiconductor device die; and the first RLEM, the semiconductor device die, and a portion of the substrate leads covered with mold compound and forming a packaged semiconductor device die.
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公开(公告)号：US20200043753A1
公开(公告)日：2020-02-06
申请号：US16653536
申请日：2019-10-15
IPC分类号： H01L21/56 , H01L23/29 , H01L23/495 , C08G59/18 , H01L23/64 , H01L23/522 , H01L23/00 , H01L23/50 , H01L23/31
摘要： A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.
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公开(公告)号：US20160181225A1
公开(公告)日：2016-06-23
申请号：US15012907
申请日：2016-02-02
IPC分类号： H01L23/00
CPC分类号： H01L24/85 , H01L21/56 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05624 , H01L2224/45144 , H01L2224/45147 , H01L2224/48227 , H01L2224/4845 , H01L2224/48507 , H01L2224/48824 , H01L2224/85035 , H01L2224/85205 , H01L2224/85948 , H01L2924/00014 , H01L2924/3862 , H01L2924/013 , H01L2924/01029 , H01L2924/01028 , H01L2924/01079 , H01L2224/45015 , H01L2924/207
摘要： A method for fabricating a semiconductor device is disclosed. A packaged semiconductor device is provided having copper ball bonds attached to aluminum pads. The packaged device is treated for at least one cycle at a temperature in the range from about 250° C. to 270° C. for a period of time in the range from about 20 s to 40 s.
摘要翻译： 公开了一种制造半导体器件的方法。 提供了一种封装的半导体器件，其具有连接到铝焊盘的铜球焊接。 将包装的装置在约250℃至270℃的温度下处理至少一个循环，持续约20秒至40秒的时间。
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公开(公告)号：US11430747B2
公开(公告)日：2022-08-30
申请号：US17192511
申请日：2021-03-04
摘要： A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.
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公开(公告)号：US20220208695A1
公开(公告)日：2022-06-30
申请号：US17192511
申请日：2021-03-04
摘要： A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.
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