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公开(公告)号：US10819294B1
公开(公告)日：2020-10-27
申请号：US16574231
申请日：2019-09-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sovan Ghosh , Amal Kumar Kundu , Laxmi Vivek Tripurari , Anand Subramanian
Abstract: A circuit includes first and second gain stages and an output transistor. The second gain stage includes a transconductance amplifier and a variable impedance circuit coupled to an output of the transconductance amplifier. The variable impedance circuit is configured to implement a first impedance level at frequencies below a first frequency threshold and to implement a second impedance level at frequencies above a second frequency level. The first impedance level is larger than the second impedance level. The output transistor has a control input coupled to the variable impedance circuit. At frequencies above the second frequency threshold, the second impedance level is configured to be inversely related to current through the output transistor.
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公开(公告)号：US10886933B1
公开(公告)日：2021-01-05
申请号：US16656913
申请日：2019-10-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sovan Ghosh , Minkle Eldho Paul , Laxmi Vivek Tripurari , Amal Kumar Kundu
Abstract: An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.
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3.发明授权公开(公告)号：US10447290B2
公开(公告)日：2019-10-15
申请号：US15837040
申请日：2017-12-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sovan Ghosh , Amal Kumar Kundu , Janakiraman Seetharaman
Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.
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公开(公告)号：US20240291484A1
公开(公告)日：2024-08-29
申请号：US18115657
申请日：2023-02-28
Applicant: Texas Instruments Incorporated
Inventor： Sovan Ghosh , Visvesvaraya Appala Pentakota
IPC: H03K17/687 , H03K5/01
CPC classification number: H03K17/6872 , H03K5/01 , H03K2005/00078 , H03M1/12
Abstract: An example apparatus includes a first transistor configured to receive an analog voltage signal; a second transistor configured to receive a first control signal, coupled to the first transistor, and coupled to a first terminal; a third transistor configured to receive a second control signal, receive a supply voltage, and coupled to the first terminal; a capacitor coupled to the first terminal and to ground; a fourth transistor configured to receive a third control signal and coupled to the first terminal; a fifth transistor gate configured to receive a bias voltage, coupled to ground, and coupled to the fourth transistor; a sixth transistor coupled to the fourth transistor and to ground; a seventh transistor configured to receive the supply voltage, coupled to the first terminal and to the sixth transistor; and an eighth transistor coupled to the first terminal, to the sixth transistor, and to ground.
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公开(公告)号：US11349492B2
公开(公告)日：2022-05-31
申请号：US17112095
申请日：2020-12-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sovan Ghosh , Minkle Eldho Paul , Laxmi Vivek Tripurari , Amal Kumar Kundu
Abstract: An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.
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Patent Agency Ranking
6.发明授权公开(公告)号：US10727852B2
公开(公告)日：2020-07-28
申请号：US16555265
申请日：2019-08-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sovan Ghosh , Amal Kumar Kundu , Janakiraman Seetharaman
Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.
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公开(公告)号：US20250080096A1
公开(公告)日：2025-03-06
申请号：US18241080
申请日：2023-08-31
Applicant: Texas Instruments Incorporated
Inventor： Sovan Ghosh , Visvesvaraya Appala Pentakota
Abstract: An example apparatus includes programmable circuitry configured to: provide a sample signal, a time amplification (TA) signal, and a kick signal to sample and conversion circuitry; sample a differential signal for a first amount of time-based on the sample signal; charge a first capacitor for a second amount of time-based on the first kick signal; after the first amount of time and the second amount of time, charge a second capacitor, the charging based on the first TA signal, the charging to cause a falling edge in a first delay signal; and generating, a rising edge in the delay signal based on the falling edge of O_RST signal.
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8.发明授权公开(公告)号：US11095300B2
公开(公告)日：2021-08-17
申请号：US16904604
申请日：2020-06-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sovan Ghosh , Amal Kumar Kundu , Janakiraman Seetharaman
Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.
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9.发明申请公开(公告)号：US20200321970A1
公开(公告)日：2020-10-08
申请号：US16904604
申请日：2020-06-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sovan Ghosh , Amal Kumar Kundu , Janakiraman Seetharaman
Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.
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公开(公告)号：US11527999B2
公开(公告)日：2022-12-13
申请号：US17027093
申请日：2020-09-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sovan Ghosh , Amal Kumar Kundu , Laxmi Vivek Tripurari , Anand Subramanian
Abstract: A circuit includes first and second gain stages and an output transistor. The second gain stage includes a transconductance amplifier and a variable impedance circuit coupled to an output of the transconductance amplifier. The variable impedance circuit is configured to implement a first impedance level at frequencies below a first frequency threshold and to implement a second impedance level at frequencies above a second frequency level. The first impedance level is larger than the second impedance level. The output transistor has a control input coupled to the variable impedance circuit. At frequencies above the second frequency threshold, the second impedance level is configured to be inversely related to current through the output transistor.
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