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公开(公告)号：US20200169284A1
公开(公告)日：2020-05-28
申请号：US16521170
申请日：2019-07-24
Applicant: Texas Instruments Incorporated
Inventor： Sri Navaneethakrishnan Easwaran , Ted F. Lekan , Michael J. Zroka , Darren J. Rollman
Abstract: Multiple sensors are coupled to a first pin of a PSI5 transceiver to receive a sensor bus signal. A Manchester decoder is coupled to a second pin and a battery is coupled to a third pin. A comparator receives a first voltage that is proportional to a current on the sensor bus signal and a second voltage that is proportional to a base current on the sensor bus signal and sends a data output signal to the second pin. A sample-and-hold circuit captures a third voltage used to effect the second voltage responsive to a high value on a base current sampling signal. A base-current-renewal circuit detects edge transitions on the data output signal and when the data output signal has no edge transitions for a period of time greater than a gap time defined in a PSI5 standard, sets the base current sampling signal high.
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公开(公告)号：US20170237461A1
公开(公告)日：2017-08-17
申请号：US15211039
申请日：2016-07-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sri Navaneethakrishnan Easwaran
CPC classification number: H04B1/40 , H03F1/0227 , H03F3/193 , H03F3/245 , H03F3/301 , H03F2200/18 , H03F2200/249 , H03F2200/451 , H04L67/12
Abstract: One example includes an amplifier system. The amplifier system includes an input stage configured to receive an input pulse signal and to generate a reference voltage pulse based on the input pulse signal. The amplifier system also includes an amplifier stage that receives at least one power voltage and is configured to amplify the reference voltage pulse and to provide pulse-shaping of the amplified reference voltage pulse based on a change of amplitude of the at least one power voltage resulting from an amplitude of the reference voltage pulse.
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公开(公告)号：US20240313768A1
公开(公告)日：2024-09-19
申请号：US18306378
申请日：2023-04-25
Applicant: Texas Instruments Incorporated
Inventor： Sri Navaneethakrishnan Easwaran , Angelo Pereira , Yueming Sun , Kae Wong , Ahmed E Hashim , Artur Lewinski
IPC: H03K17/687 , H03K17/10 , H03K17/567
CPC classification number: H03K17/687 , H01L27/02 , H03K17/102 , H03K17/567
Abstract: Described embodiments include a voltage converter power circuit having a high-voltage rated first transistor with a first current terminal coupled to an input voltage terminal, and a second current terminal. A second transistor, a low-voltage rated transistor, has a second control terminal, a third current terminal coupled to the second current terminal, and a fourth current terminal coupled to a switching terminal. A third transistor, a high-voltage rated transistor, has a fifth current terminal coupled to the switching terminal, a sixth current terminal, and a third control terminal. A fourth transistor, a low-voltage rated transistor, is coupled between the sixth current terminal and a ground terminal. A bleeder circuit is coupled between the seventh and eighth current terminals and is configured to prevent a voltage across the fourth transistor from exceeding a breakdown voltage.
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公开(公告)号：US10784917B2
公开(公告)日：2020-09-22
申请号：US16521170
申请日：2019-07-24
Applicant: Texas Instruments Incorporated
Inventor： Sri Navaneethakrishnan Easwaran , Ted F. Lekan , Michael J. Zroka , Darren J. Rollman
Abstract: Multiple sensors are coupled to a first pin of a PSI5 transceiver to receive a sensor bus signal. A Manchester decoder is coupled to a second pin and a battery is coupled to a third pin. A comparator receives a first voltage that is proportional to a current on the sensor bus signal and a second voltage that is proportional to a base current on the sensor bus signal and sends a data output signal to the second pin. A sample-and-hold circuit captures a third voltage used to effect the second voltage responsive to a high value on a base current sampling signal. A base-current-renewal circuit detects edge transitions on the data output signal and when the data output signal has no edge transitions for a period of time greater than a gap time defined in a PSI5 standard, sets the base current sampling signal high.
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公开(公告)号：US20190025866A1
公开(公告)日：2019-01-24
申请号：US15832071
申请日：2017-12-05
Applicant: Texas Instruments Incorporated
Inventor： Sri Navaneethakrishnan Easwaran , Vijayalakshmi Devarajan , Timothy Paul Duryea , Shanmuganand Chellamuthu
IPC: G05F3/26 , H03K17/687 , B60T8/1761 , B60T8/172
Abstract: A current sink circuit coupled to pull down a gate control node (GCN) for an NMOS power FET that controls an actuator includes first and second NMOS transistors coupled in series between the GCN and a lower rail, where the first NMOS transistor has a gate and drain coupled together through a resistor. The current sink circuit also includes a control signal generation circuit (CSGC) and a negative voltage blocking circuit (NVBC). The CSGC is coupled to receive at least one voltage input and an ignition signal and to provide a first control signal and a second control signal. The NVBC is coupled to pass the first control signal from the control signal generation circuit to the gate of the first NMOS transistor and to block a negative voltage on the GCN from reaching the CSGC. The second control signal is coupled to the gate of the second NMOS transistor.
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Patent Agency Ranking
公开(公告)号：US11469788B2
公开(公告)日：2022-10-11
申请号：US16991553
申请日：2020-08-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sri Navaneethakrishnan Easwaran , Ted F. Lekan , Michael J. Zroka , Darren J. Rollman
Abstract: Multiple sensors are coupled to a first pin of a PSI5 transceiver to receive a sensor bus signal. A Manchester decoder is coupled to a second pin and a battery is coupled to a third pin. A comparator receives a first voltage that is proportional to a current on the sensor bus signal and a second voltage that is proportional to a base current on the sensor bus signal and sends a data output signal to the second pin. A sample-and-hold circuit captures a third voltage used to effect the second voltage responsive to a high value on a base current sampling signal. A base-current-renewal circuit detects edge transitions on the data output signal and when the data output signal has no edge transitions for a period of time greater than a gap time defined in a PSI5 standard, sets the base current sampling signal high.
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公开(公告)号：US10804691B2
公开(公告)日：2020-10-13
申请号：US15913465
申请日：2018-03-06
Applicant: Texas Instruments Incorporated
Inventor： Sri Navaneethakrishnan Easwaran , Timothy Paul Duryea
IPC: H02H3/00 , H03K17/687 , H04B1/40 , H03F3/45
Abstract: An electronic control unit (ECU) operates between first and second voltage rails and includes an amplifier circuit and a single current sense circuit coupled to carry a signal to a bus pin and to protect the bus pin from both a short to ground and a short to battery. The single current sense circuit includes a switch circuit that passes the signal to the bus pin and a forward current sensing circuit that provides a second current that is proportional to an output current at the bus pin. The forward current sensing circuit causes the second current to be substantially zero when voltage on the bus pin is above a given value. The single current sense circuit also includes a forward current protection circuit and a reverse current switching circuit that receives the second current and closes a connection to the second voltage when the second current is zero.
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公开(公告)号：US20180073895A1
公开(公告)日：2018-03-15
申请号：US15263114
申请日：2016-09-12
Applicant: Texas Instruments Incorporated
Abstract: An angular resolver system includes, for example, an imbalance detector for detecting degraded resolver output signals. The imbalance detector includes a first and second power averaging circuits and a comparator circuit. The first power averaging circuit includes a first integrator for generating over a first time window a first average power signal in response to resolver sensor output signals. The second power averaging circuit includes a second integrator for generating over a second time window a second average power signal in response to the resolver sensor output signals, where the first time window is longer than the second time window. The comparator circuit compares the first average power signal and the second average power signal and generates a fault signal when the first average power signal and the second average power signal differ by a selected voltage threshold.
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公开(公告)号：US09710002B2
公开(公告)日：2017-07-18
申请号：US14930906
申请日：2015-11-03
Applicant: Texas Instruments Incorporated
Abstract: Dynamic biasing circuits for low drop out (LDO) regulators are described. In some embodiments, an electronic circuit may include a low drop out (LDO) regulator; and a biasing circuit coupled to the LDO regulator, the biasing circuit configured to: monitor a first electrical current and a second electrical current; select a greater of the first or second electrical currents; and provide the selected electrical current to the LDO regulator. In other embodiments, a method may include: providing a digital core and a low drop out (LDO) regulator coupled to the digital core, wherein the digital core is configured to operate in an active mode and in a standby mode; monitoring, via a current selector circuit coupled to the LDO regulator, a first current and a second current; selecting a greater of the first or second electrical currents; and providing the selected current as a biasing current to the LDO regulator.
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公开(公告)号：US10884037B2
公开(公告)日：2021-01-05
申请号：US15263114
申请日：2016-09-12
Applicant: Texas Instruments Incorporated
Abstract: An angular resolver system includes, for example, an imbalance detector for detecting degraded resolver output signals. The imbalance detector includes a first and second power averaging circuits and a comparator circuit. The first power averaging circuit includes a first integrator for generating over a first time window a first average power signal in response to resolver sensor output signals. The second power averaging circuit includes a second integrator for generating over a second time window a second average power signal in response to the resolver sensor output signals, where the first time window is longer than the second time window. The comparator circuit compares the first average power signal and the second average power signal and generates a fault signal when the first average power signal and the second average power signal differ by a selected voltage threshold.
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