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    Serial bus repeater with low power state detection
    2.
    发明授权
    Serial bus repeater with low power state detection 有权

    公开(公告)号：US12135676B2

    公开(公告)日：2024-11-05

    申请号：US17348813

    申请日：2021-06-16

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Win Naing Maung ,  Suzanne Mary Vining

    IPC: G06F13/42 ,  G06F1/3206 ,  G06F13/38

    Abstract: A serial bus repeater includes a port circuit and a low power state detection circuit. The port circuit is configured to communicate via a serial bus. The low power state detection circuit includes a power state transaction identification circuit and a bus state identification circuit. The power state transaction identification circuit is configured to identify a power state transaction on the serial bus. The power state transaction is indicative of entering a reduced power state. The bus state identification circuit is configured to identify a value of termination resistance on the serial bus that is indicative of entering the reduced power state.

    Serial bus signal conditioner for detecting initiation of or return to high-speed signaling
    5.
    发明授权
    Serial bus signal conditioner for detecting initiation of or return to high-speed signaling 有权

    公开(公告)号：US11580053B2

    公开(公告)日：2023-02-14

    申请号：US17347920

    申请日：2021-06-15

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Win Naing Maung ,  Suzanne Mary Vining ,  Yonghui Tang ,  Douglas Edward Wente ,  Huanzhang Huang

    IPC: G06F13/42

    Abstract: A serial bus signal conditioner circuit includes receiver circuitry, a mode identification circuit, and an edge-rate booster circuit. The receiver circuitry is configured to receive signals transmitted on a serial bus. The mode identification circuit is coupled to the receiver circuitry, and is configured to identify initiation of or return to high-speed signaling on the serial bus based on sequences of the signals transmitted on the serial bus. The edge-rate booster circuit is coupled to the mode identification circuit, and is configured to identify edges of a differential signal transmitted on the serial bus, and to supply a differential current to the serial bus based on identification of an edge of the differential signal.

    Bi-level adaptive equalizer
    7.
    发明授权
    Bi-level adaptive equalizer 有权

    公开(公告)号：US11038723B2

    公开(公告)日：2021-06-15

    申请号：US16778955

    申请日：2020-01-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Amit Rane ,  Charles Michael Campbell ,  Suzanne Mary Vining

    IPC: H04L25/03 ,  H04L7/00 ,  G11B20/10

    Abstract: At least some aspects of the present disclosure provide for a method. In at least one example, the method includes applying first equalization to a received data signal to generate an equalizer signal and comparing the equalized signal to each of a plurality of reference voltages for a predetermined period of time per respective reference voltage to generate a comparison result. The method further includes determining a plurality of counts with each count of the plurality of counts uniquely corresponding to a number of rising edges in the comparison result for each of the plurality of reference voltages. The method further includes comparing at least one of the plurality of counts to at least another of the plurality of counts to determine a relationship among the plurality of counts and applying second equalization to the received data signal based on the determined relationship among the plurality of counts.

    Adaptive equalizer for redriver
    9.
    发明授权
    Adaptive equalizer for redriver 有权

    公开(公告)号：US11533205B2

    公开(公告)日：2022-12-20

    申请号：US17402118

    申请日：2021-08-13

    Applicant: Texas Instruments Incorporated

    Inventor： Suzanne Mary Vining ,  Amit S. Rane ,  Charles Michael Campbell

    IPC: H04L25/03

    Abstract: A system for selecting an equalizer setting of an equalizer to equalize signals received via a communications link. Starting with a first (e.g., minimum) equalizer setting and a threshold voltage near the mid-eye voltage of the equalized output signal, the system estimates the amplitude of the inner eye of the equalized output signal by comparing the equalized output signal to a series of threshold voltages. If the amplitude of the equalized output signal is less than ideal, the system dynamically increases the equalizer setting. The system quickly converges on the equalizer setting for the communication link because, rather than comparing the output signal at every voltage offset using every equalizer setting, the system only evaluates the equalizer settings necessary to select the equalizer setting for the communications link and uses only the voltage offsets necessary to evaluate each equalizer setting.

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