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    Single inductor multiple output regulator
    2.
    发明授权
    Single inductor multiple output regulator 有权

    公开(公告)号：US11190105B1

    公开(公告)日：2021-11-30

    申请号：US17119862

    申请日：2020-12-11

    Applicant: Texas Instruments Incorporated

    Inventor： Vipul Kumar Singhal ,  RR Manikandan ,  Rajat Chauhan ,  Vinod Joseph Menezes

    IPC: H02M1/08 ,  H02M3/157 ,  H02M3/158 ,  H02M1/00

    Abstract: An electronic device having multiple power output circuits that individually include a switch control input, a bypass control input, an output transistor and an output control circuit that includes an RC circuit with a resistor and a capacitor coupled to the output transistor gate and a bypass switch in parallel with the RC circuit resistor. The electronic device includes a controller that selects one of the power output circuits for a given power transfer cycle, closes the bypass switch to bypass the resistor of the selected power output circuit and turns the output transistor of the selected power output circuit on to transfer current from the inductor to a load of the selected power output circuit.

    LOW LEAKAGE SHADOW LATCH-BASED MULTI-THRESHOLD CMOS SEQUENTIAL CIRCUIT
    3.
    发明申请
    LOW LEAKAGE SHADOW LATCH-BASED MULTI-THRESHOLD CMOS SEQUENTIAL CIRCUIT 有权
    基于低漏电阴极保护的多阈值CMOS序列电路

    公开(公告)号：US20160065188A1

    公开(公告)日：2016-03-03

    申请号：US14521853

    申请日：2014-10-23

    Applicant: Texas Instruments Incorporated

    Inventor： Vipul Kumar Singhal

    IPC: H03K3/3562 ,  H03K3/012

    CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/356008

    Abstract: Multi-threshold CMOS (MTCMOS) sequential circuits are presented with a first latch circuit formed of transistors with threshold voltages in a first range, along with a second latch circuit with inverters and a transfer gate formed of higher threshold voltage transistors for low-power retention of data from the first latch with power switching circuitry to selectively decouple inverters of the second latch circuit from a voltage supply during low-power retention mode operation of the sequential circuit.

    Abstract translation: 多阈值CMOS（MTCMOS）时序电路具有由具有第一范围内的阈值电压的晶体管形成的第一锁存电路，以及具有反相器的第二锁存电路和由用于低功率保持的较高阈值电压晶体管形成的传输门 来自具有功率开关电路的第一锁存器的数据，以在顺序电路的低功率保持模式操作期间选择性地将第二锁存电路的反相器与电压源分离。

    Load current measurement
    4.
    发明授权
    Load current measurement 有权

    公开(公告)号：US10855184B2

    公开(公告)日：2020-12-01

    申请号：US16601143

    申请日：2019-10-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Vinod Joseph Menezes ,  Manikandan Rr ,  Rajat Chauhan ,  Vipul Kumar Singhal ,  Mahesh Madhukar Mehendale ,  Kaichien Tsai

    IPC: G05F3/24 ,  G05F1/573 ,  G05F1/46 ,  H02M3/158 ,  G01R19/165 ,  H02M1/00 ,  G05F1/575

    Abstract: A switch-mode power supply includes a DC-DC converter and metering circuitry that is coupled to the DC-DC converter. The metering circuitry includes scaling circuitry, a current source, a capacitor, switching circuitry, and a comparator. The scaling circuitry is configured to generate a reference current scaled to be a predetermined fraction of a peak current flowing in an inductor of the DC-DC converter. The current source is configured to output a first current that is one-half of the reference current. The capacitor is coupled to the current source. The switching circuitry is configured to switchably connect the current source to the capacitor. The comparator is coupled to the capacitor. The comparator is configured to generate a signal indicating that a voltage across the capacitor exceeds a threshold voltage.

    Mode-Variant Adaptive Body Bias Scheme For Low-Power Semiconductors
    5.
    发明申请
    Mode-Variant Adaptive Body Bias Scheme For Low-Power Semiconductors 审中-公开
    用于低功率半导体的模式变型自适应体偏置方案

    公开(公告)号：US20160071849A1

    公开(公告)日：2016-03-10

    申请号：US14624323

    申请日：2015-02-17

    Applicant: Texas Instruments Incorporated

    Inventor： Vipul Kumar Singhal

    IPC: H01L27/092 ,  H03K3/012

    CPC classification number: H01L27/092 ,  H03K19/0013 ,  H03K19/0027

    Abstract: A complementary metal oxide semiconductor (CMOS) device having an active mode and a standby mode. The CMOS device includes a first transistor having a first body, a second transistor having a second body, a first forward body bias voltage source, and a second forward body bias voltage source. The first forward body bias voltage source is coupled to the first body when the CMOS device is in the active mode, and is disconnected from the first body when the CMOS device is in the standby mode. The second forward body bias voltage source is coupled to the second body when the CMOS device is in the active mode, and is disconnected from the second body when the CMOS device is in the standby mode.

    Abstract translation: 具有活动模式和待机模式的互补金属氧化物半导体（CMOS）器件。 CMOS器件包括具有第一本体的第一晶体管，具有第二主体的第二晶体管，第一正向偏置电压源和第二正向偏置电压源。 当CMOS器件处于活动模式时，第一正向偏置电压源耦合到第一主体，并且当CMOS器件处于待机模式时，第一正向偏置电压源与第一主体相连。 当CMOS器件处于激活模式时，第二正向偏置电压源耦合到第二主体，并且当CMOS器件处于待机模式时，第二正向偏置电压源与第二主体耦合。

    Low leakage shadow latch-based multi-threshold CMOS sequential circuit
    6.
    发明授权
    Low leakage shadow latch-based multi-threshold CMOS sequential circuit 有权
    基于低泄漏阴影锁存的多阈值CMOS时序电路

    公开(公告)号：US09287858B1

    公开(公告)日：2016-03-15

    申请号：US14521853

    申请日：2014-10-23

    Applicant: Texas Instruments Incorporated

    Inventor： Vipul Kumar Singhal

    IPC: H03K3/289 ,  H03K3/3562 ,  H03K3/012

    CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/356008

    Abstract: Multi-threshold CMOS (MTCMOS) sequential circuits are presented with a first latch circuit formed of transistors with threshold voltages in a first range, along with a second latch circuit with inverters and a transfer gate formed of higher threshold voltage transistors for low-power retention of data from the first latch with power switching circuitry to selectively decouple inverters of the second latch circuit from a voltage supply during low-power retention mode operation of the sequential circuit.

    Abstract translation: 多阈值CMOS（MTCMOS）时序电路具有由具有第一范围内的阈值电压的晶体管形成的第一锁存电路，以及具有反相器的第二锁存电路和由用于低功率保持的较高阈值电压晶体管形成的传输门 来自具有功率开关电路的第一锁存器的数据，以在顺序电路的低功率保持模式操作期间选择性地将第二锁存电路的反相器与电压源分离。

    Dual edge-triggered retention flip-flop
    7.
    发明授权
    Dual edge-triggered retention flip-flop 有权
    双边沿触发保持触发器

    公开(公告)号：US09276566B2

    公开(公告)日：2016-03-01

    申请号：US14468343

    申请日：2014-08-26

    Applicant: Texas Instruments Incorporated

    Inventor： Vipul Kumar Singhal

    IPC: H03K3/289 ,  H03K3/037 ,  H03K19/00

    CPC classification number: H03K3/0375 ,  H03K19/0013

    Abstract: A dual edge triggered retention flip-flop reduces clock tree power dissipation in an active mode and leakage power in a low-power (e.g., standby) mode. For example, a first latch can be used to latch a first state of an input to a flip-flop in response to a first (e.g., positive-going) edge of a clock signal and a second latch can be used to latch a second state of the input to the flip-flop in response to a second (e.g., negative-going) edge of a clock signal. A retention latch can be used to latch and retain the state of the flip-flop when the first and second latches are disabled to save power in the low-power mode. The retention latch can also be used to initialize at least one of the first and second flip-flops when exiting the low-power mode.

    Abstract translation: 双边沿触发保持触发器在低功耗（例如，待机）模式下降低主动模式下的时钟树功耗和泄漏功率。 例如，可以使用第一锁存器来响应于时钟信号的第一（例如正向）边沿来将输入的第一状态锁存到触发器，并且可以使用第二锁存器来锁存第二锁存器 响应于时钟信号的第二（例如负向）边沿对触发器的输入状态。 当禁用第一和第二锁存器以在低功率模式下节省功率时，保持锁存器可用于锁存和保持触发器的状态。 当退出低功率模式时，保持锁存器也可用于初始化第一和第二触发器中的至少一个。

    Power-on reset circuit
    10.
    发明授权
    Power-on reset circuit 有权

    公开(公告)号：US10432192B1

    公开(公告)日：2019-10-01

    申请号：US16110892

    申请日：2018-08-23

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Divya Kaur ,  Rajat Chauhan ,  Vipul Kumar Singhal

    IPC: H03K17/22 ,  H03K17/14 ,  H03K3/3565

    Abstract: A circuit includes an input stage that includes a first transistor device configured to generate a first output signal in response to a first bias current activating the first transistor device by exceeding a first threshold voltage of the first transistor device. A compensation stage includes a second transistor device coupled with a third transistor device. The second transistor device is activated in response to the first output signal exceeding a second threshold voltage of the second transistor device. The third transistor device is activated in response to activation of the second transistor device and a second bias current. The compensation stage is configured to generate a second output signal in response to the activation of the third transistor device. An output stage is configured to generate a reset signal in response to the second output signal exceeding a third threshold voltage.

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