公开(公告)号：US07180154B2

公开(公告)日：2007-02-20

申请号：US10845048

申请日：2004-05-13

申请人： Tai-Heui Cho ,  Hyuck-Jin Kang ,  Heui-Won Shin ,  Gwang-Seon Byun ,  Sun-Joon Kim

发明人： Tai-Heui Cho ,  Hyuck-Jin Kang ,  Heui-Won Shin ,  Gwang-Seon Byun ,  Sun-Joon Kim

IPC分类号： H01L29/00

CPC分类号： H01L23/5258 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Integrated circuit devices are provided including an integrated circuit substrate and first through fourth spaced apart lower interconnects on the integrated circuit substrate. The third and fourth spaced apart lower interconnects are parallel to the first and second lower interconnects. A first fuse is provided on the first and second lower interconnects between the first and second lower interconnects and is electrically coupled to the first and second lower interconnects. A second fuse is provided spaced apart from the first fuse and on the third and fourth lower interconnects. The second fuse is between the third and fourth lower interconnects and is electrically coupled to the third and fourth lower interconnects. Related methods of fabricating integrated circuit devices are also provided.

公开(公告)号：US20070114635A1

公开(公告)日：2007-05-24

申请号：US11651264

申请日：2007-01-09

申请人： Tai-Heui Cho ,  Hyuck-Jin Kang ,  Heui-Won Shin ,  Gwang-Seon Byun ,  Sun-Joon Kim

发明人： Tai-Heui Cho ,  Hyuck-Jin Kang ,  Heui-Won Shin ,  Gwang-Seon Byun ,  Sun-Joon Kim

IPC分类号： H01L29/00 ,  H01L21/331

CPC分类号： H01L23/5258 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Integrated circuit devices are provided including an integrated circuit substrate and first through fourth spaced apart lower interconnects on the integrated circuit substrate. The third and fourth spaced apart lower interconnects are parallel to the first and second lower interconnects. A first fuse is provided on the first and second lower interconnects between the first and second lower interconnects and is electrically coupled to the first and second lower interconnects. A second fuse is provided spaced apart from the first fuse and on the third and fourth lower interconnects. The second fuse is between the third and fourth lower interconnects and is electrically coupled to the third and fourth lower interconnects. Related methods of fabricating integrated circuit devices are also provided.

摘要翻译： 提供集成电路器件，其包括集成电路衬底和集成电路衬底上的第一至第四间隔开的下部互连。 第三和第四间隔开的下互连平行于第一和第二下互连。 第一保险丝设置在第一和第二下互连之间的第一和第二下互连上，并且电耦合到第一和第二下互连。 第二保险丝设置成与第一保险丝隔开并且在第三和第四下部互连上。 第二保险丝在第三和第四下部互连之间，并且电耦合到第三和第四下部互连。 还提供了制造集成电路器件的相关方法。

公开(公告)号：US06984895B2

公开(公告)日：2006-01-10

申请号：US10125598

申请日：2002-04-19

申请人： Tai-Heui Cho ,  Hyuck-Jin Kang ,  Min-Chul Kim ,  Byung-Yoon Kim

发明人： Tai-Heui Cho ,  Hyuck-Jin Kang ,  Min-Chul Kim ,  Byung-Yoon Kim

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L23/585 ,  H01L24/03 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2224/05082 ,  H01L2224/05093 ,  H01L2224/05124 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043

摘要： A bonding pad structure in an integrated circuit (IC) and a method for manufacturing thereof comprises a plurality of dummy patterns deposited in sub-layers of the IC, each dummy pattern being connected via a metal link to a plurality of complementary top surface bonding pads, wherein the dummy patterns and the metal link are constructed during the same process steps used to construct the circuit elements included in the IC, without additional or special process steps. Such an imbedded and anchored bonding pad provides contact reliability for both conductive and non-conductive pads used for the interconnection of integrated circuits in a manner that resists layer separation or de-lamination under pulling stresses that are present on the bonding pads.

摘要翻译： 集成电路（IC）中的焊盘结构及其制造方法包括沉积在IC的子层中的多个虚拟图案，每个虚设图案通过金属连接件连接到多个互补顶表面焊盘 其中虚设图案和金属连接件在用于构造包括在IC中的电路元件的相同工艺步骤中构成，而无需额外的或特殊的工艺步骤。 这种嵌入式和固定式焊接垫为在集成电路的互连中使用的导电和非导电焊盘提供了接触可靠性，以抵抗在接合焊盘上存在的拉应力下的层分离或去层压。

公开(公告)号：US06867070B2

公开(公告)日：2005-03-15

申请号：US10358139

申请日：2003-02-05

申请人： Tai-Heui Cho ,  Hyuck-Jin Kang ,  Min-Chul Kim ,  Byung-Yoon Kim

发明人： Tai-Heui Cho ,  Hyuck-Jin Kang ,  Min-Chul Kim ,  Byung-Yoon Kim

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/58 ,  H01L27/108 ,  H01L21/44

CPC分类号： H01L24/05 ,  H01L23/585 ,  H01L24/03 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2224/05082 ,  H01L2224/05093 ,  H01L2224/05124 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043

摘要： A bonding pad structure in an integrated circuit (IC) and a method for manufacturing thereof comprises a plurality of dummy patterns deposited in sub-layers of the IC, each dummy pattern being connected via a metal link to a plurality of complementary top surface bonding pads, wherein the dummy patterns and the metal link are constructed during the same process steps used to construct the circuit elements included in the IC, without additional or special process steps. Such an imbedded and anchored bonding pad provides contact reliability for both conductive and non-conductive pads used for the interconnection of integrated circuits in a manner that resists layer separation or de-lamination under pulling stresses that are present on the bonding pads.

摘要翻译： 集成电路（IC）中的焊盘结构及其制造方法包括沉积在IC的子层中的多个虚拟图案，每个虚设图案通过金属连接件连接到多个互补顶表面焊盘 其中虚设图案和金属连接件在用于构造包括在IC中的电路元件的相同工艺步骤中构成，而无需额外的或特殊的工艺步骤。 这种嵌入式和固定式焊接垫为在集成电路的互连中使用的导电和非导电焊盘提供了接触可靠性，以抵抗在接合焊盘上存在的拉应力下的层分离或去层压。

公开(公告)号：US07556989B2

公开(公告)日：2009-07-07

申请号：US11387158

申请日：2006-03-22

申请人： Tai-Heui Cho ,  Kun-Gu Lee

发明人： Tai-Heui Cho ,  Kun-Gu Lee

IPC分类号： H01L21/82 ,  H01L21/311

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and a first capping pattern, an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse pattern, and a second insulating layer formed on the first insulating layer and covering the fuse pattern.

摘要翻译： 半导体器件包括具有熔丝区域和互连区域的半导体衬底，形成在熔丝区域和互连区域中的第一绝缘层，形成在熔丝区域中的第一绝缘层上的熔丝图案，熔丝图案包括第一 导电图案和第一封盖图案，形成在互连区域中的第一绝缘层上的互连图案，包括第二导电图案和第二封盖图案，并且具有大于熔丝图案的厚度的厚度，以及第二绝缘体 层，形成在第一绝缘层上并覆盖熔丝图案。

公开(公告)号：US20070269979A1

公开(公告)日：2007-11-22

申请号：US11656510

申请日：2007-01-23

申请人： Tai-Heui Cho

发明人： Tai-Heui Cho

IPC分类号： H01L21/8242

CPC分类号： H01L21/76897 ,  H01L21/32134 ,  H01L21/76831 ,  H01L21/76834 ,  H01L27/10814 ,  H01L27/10885

摘要： A method of forming a tungsten pattern includes forming a preliminary tungsten pattern on a substrate and partially removing a surface of the preliminary tungsten pattern using deionized water to form the tungsten pattern.

摘要翻译： 形成钨图案的方法包括在基板上形成预备钨图案，并使用去离子水部分去除预备钨图案的表面以形成钨图案。

公开(公告)号：US20060214260A1

公开(公告)日：2006-09-28

申请号：US11387158

申请日：2006-03-22

申请人： Tai-Heui Cho ,  Kun-Gu Lee

发明人： Tai-Heui Cho ,  Kun-Gu Lee

IPC分类号： H01L29/00

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and a first capping pattern, an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse pattern, and a second insulating layer formed on the first insulating layer and covering the fuse pattern.