公开(公告)号：US09647087B2

公开(公告)日：2017-05-09

申请号：US14843720

申请日：2015-09-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mei-Chun Chen ,  Ching-Chen Hao ,  Wen-Hsin Chan ,  Chao-Jui Wang

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/40 ,  H01L21/28 ,  H01L29/78 ,  H01L21/768 ,  H01L23/485 ,  H01L21/311 ,  H01L21/3115 ,  H01L29/51

CPC classification number: H01L21/28247 ,  H01L21/28123 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/408 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate with a gate stack formed on the semiconductor substrate. The method also includes forming a protection layer doped with a quadrivalent element to cover a first doped region formed in the semiconductor substrate and adjacent to the gate stack. The method further includes forming a main spacer layer on a sidewall of the gate stack to cover the protection layer and forming an insulating layer over the protection layer. In addition, the method includes forming an opening in the insulating layer to expose a second doped region formed in the semiconductor substrate and forming one contact in the opening.

公开(公告)号：US09991123B2

公开(公告)日：2018-06-05

申请号：US15584650

申请日：2017-05-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mei-Chun Chen ,  Ching-Chen Hao ,  Wen-Hsin Chan ,  Chao-Jui Wang

IPC: H01L23/48 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L23/485 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L21/28247 ,  H01L21/28123 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/408 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate including a first doped region and a second doped region and a gate stack on the semiconductor substrate. The semiconductor device also includes a main spacer layer on a sidewall of the gate stack and a protection layer between the main spacer layer and the semiconductor substrate. The protection layer is doped with a quadrivalent element. The semiconductor device further includes an insulating layer formed over the semiconductor substrate and the gate stack and a contact formed in the insulating layer. The contact includes a first portion contacting the first doped region, and the contact includes a second portion contacting the second doped region. The first portion extends deeper into the semiconductor substrate than the second portion.

公开(公告)号：US09136340B2

公开(公告)日：2015-09-15

申请号：US13910610

申请日：2013-06-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mei-Chun Chen ,  Ching-Chen Hao ,  Wen-Hsin Chan ,  Chao-Jui Wang

IPC: H01L23/48 ,  H01L29/40 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L21/28247 ,  H01L21/28123 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/408 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate having a first doped region and a second doped region, and a gate stack formed on the semiconductor substrate. The semiconductor device also includes a main spacer layer formed on a sidewall of the gate stack. The semiconductor device further includes a protection layer formed between the main spacer layer and the semiconductor substrate, and the protection layer is doped with a quadrivalent element. In addition, the semiconductor device includes an insulating layer formed on the semiconductor substrate and the gate stack, and a contact formed in the insulating layer. The contact has a first portion contacting the first doped region and has a second portion contacting the second doped region. The first region extends deeper into the semiconductor substrate than the second portion.

Abstract translation: 提供了用于形成半导体器件的机构的实施例。 半导体器件包括具有第一掺杂区和第二掺杂区的半导体衬底和形成在半导体衬底上的栅叠层。 半导体器件还包括形成在栅叠层的侧壁上的主间隔层。 半导体器件还包括形成在主间隔层和半导体衬底之间的保护层，并且保护层掺杂有四价元素。 此外，半导体器件包括形成在半导体衬底和栅极堆叠上的绝缘层和形成在绝缘层中的接触。 接触件具有接触第一掺杂区域的第一部分，并且具有接触第二掺杂区域的第二部分。 第一区域比第二部分更深地延伸到半导体衬底中。

公开(公告)号：US10002802B2

公开(公告)日：2018-06-19

申请号：US15606098

申请日：2017-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Sheng-Tang Wang ,  Chia-Ming Chang ,  Shih-Che Lin ,  Chao-Jui Wang

IPC: H01L21/00 ,  H01L21/66

CPC classification number: H01L22/20 ,  H01L22/12

Abstract: Methods for reducing core-to-core mismatch are provided. The method includes measuring gate lengths of a representative pattern of each core in a first lot of SOC products by a measurement apparatus. Each of the SOC products in the first lot includes more than two cores identical to each other. The method also includes determining a tuning amount according to the differences between the gate lengths of each core, and adjusting at least one mask for critical dimensions of gate length of each core in a second lot of SOC products respectively according to the tuning amounts.

公开(公告)号：US09666495B2

公开(公告)日：2017-05-30

申请号：US14105794

申请日：2013-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Tang Wang ,  Chia-Ming Chang ,  Shih-Che Lin ,  Chao-Jui Wang

IPC: H01L21/00 ,  H01L21/66

CPC classification number: H01L22/20 ,  H01L22/12

Abstract: Methods for reducing core-to-core mismatch are provided. The method includes measuring gate lengths of a representative pattern of each core in a first lot of SOC products by a measurement apparatus. Each of the SOC products in the first lot includes more than two cores identical to each other. The method also includes determining tuning amounts according to the differences between the gate lengths of each core, and adjusting manufacturing conditions for critical dimensions of gate length of each core in a second lot of SOC products respectively according to the tuning amounts for reducing core-to-core mismatch due to the surrounding environment of each core. Each of the SOC products in the second lot includes more than two cores identical to each other and also identical to the cores in the first lot.