公开(公告)号：US20200287032A1

公开(公告)日：2020-09-10

申请号：US15930285

申请日：2020-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L29/775 ,  H01L29/205 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.

公开(公告)号：US10727427B2

公开(公告)日：2020-07-28

申请号：US16120158

申请日：2018-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Timothy Vasen ,  Mark van Dal ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L51/05 ,  H01L27/28 ,  H01L51/00

Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.

公开(公告)号：US12193318B2

公开(公告)日：2025-01-07

申请号：US17688259

申请日：2022-03-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Martin Christopher Holland ,  Timothy Vasen ,  Blandine Duriez

IPC: H10K10/84 ,  C23C16/26 ,  C30B25/02 ,  C30B29/02 ,  H10K10/46 ,  H10K85/20 ,  H10K71/10

Abstract: A method includes placing a first charged metal dot on a first position of a surface of a semiconductor substrate. A first charged region is formed on a second position of the surface of the semiconductor substrate. A precursor gas is flowed along a first direction from the first position toward the second position on the semiconductor substrate, thereby forming a first carbon nanotube (CNT) on the semiconductor substrate. A dielectric layer is deposited to cover the first CNT and the semiconductor substrate. A second charged metal dot is placed on a third position of a surface of the dielectric layer. A second charged region is formed on a fourth position of the surface of the dielectric layer. The precursor gas is flowed along a second direction from the third position toward the fourth position on the semiconductor substrate, thereby forming a second CNT on the first CNT.

公开(公告)号：US11158807B2

公开(公告)日：2021-10-26

申请号：US16656583

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Chao-Ching Cheng ,  Matthias Passlack ,  Martin Christopher Holland ,  Tse-An Chen ,  Lain-Jong Li

IPC: H01L51/00 ,  H01L51/05

Abstract: A field effect transistor includes a semiconductor substrate, a first pad layer, carbon nanotubes and a gate structure. The first pad layer is disposed over the semiconductor substrate and comprises a 2D material. The carbon nanotubes are disposed over the first insulating pad layer. The gate structure is disposed over the semiconductor substrate and is vertically stacked with the carbon nanotubes. The carbon nanotubes extend from one side to an opposite side of the gate structure.

公开(公告)号：US11088337B2

公开(公告)日：2021-08-10

申请号：US16590115

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Marcus Johannes Henricus Van Dal ,  Gerben Doornbos

IPC: H01L51/05 ,  H01L27/28 ,  H01L51/00 ,  H01L51/10

Abstract: In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.

公开(公告)号：US20220262936A1

公开(公告)日：2022-08-18

申请号：US17735985

申请日：2022-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L29/775 ,  H01L29/205 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.

公开(公告)号：US20220181565A1

公开(公告)日：2022-06-09

申请号：US17680199

申请日：2022-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Marcus Johannes Henricus Van Dal ,  Timothy Vasen ,  Gerben Doornbos

IPC: H01L51/05 ,  H01L51/00 ,  H01L27/28

Abstract: The current disclosure describes techniques for forming semiconductor structures having multiple semiconductor strips configured as channel portions. In the semiconductor structures, diffusion break structures are formed after the gate structures are formed so that the structural integrity of the semiconductor strips adjacent to the diffusion break structures will not be compromised by a subsequent gate formation process. The diffusion break extends downward from an upper surface until all the semiconductor strips of the adjacent channel portions are truncated by the diffusion break.

公开(公告)号：US11276832B2

公开(公告)日：2022-03-15

申请号：US16559341

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Marcus Johannes Henricus van Dal ,  Timothy Vasen ,  Gerben Doornbos

IPC: H01L51/05 ,  H01L51/00 ,  H01L27/28

Abstract: The current disclosure describes techniques for forming semiconductor structures having multiple semiconductor strips configured as channel portions. In the semiconductor structures, diffusion break structures are formed after the gate structures are formed so that the structural integrity of the semiconductor strips adjacent to the diffusion break structures will not be compromised by a subsequent gate formation process. The diffusion break extends downward from an upper surface until all the semiconductor strips of the adjacent channel portions are truncated by the diffusion break.

公开(公告)号：US11165032B2

公开(公告)日：2021-11-02

申请号：US16562423

申请日：2019-09-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Timothy Vasen

IPC: H01L51/05 ,  H01L27/28 ,  H01L51/00 ,  H01L51/10

Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure including carbon nanotubes (CNTs) embedded in a semiconductor layer is formed, a sacrificial gate structure is formed over the fin structure, the semiconductor layer is doped at a source/drain region of the fin structure, an interlayer dielectric (ILD) layer is formed over the doped source/drain region and the sacrificial gate structure, a source/drain opening is formed by patterning the ILD layer, and a source/drain contact layer is formed over the doped source/drain region of the fin structure.

公开(公告)号：US11004958B2

公开(公告)日：2021-05-11

申请号：US16271964

申请日：2019-02-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Blandine Duriez ,  Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Timothy Vasen

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/08 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a channel region of a semiconductor layer, a source/drain epitaxial layer is formed on opposing sides of the dummy gate structure, a planarization operation is performed on the source/drain epitaxial layer, the planarized source/drain epitaxial layer is patterned, the dummy gate structure is removed to form a gate space, and a metal gate structure is formed in the gate space.