Abstract:
A signal source device includes at least one digital-to-analog converter, at least one connector, a first output path from the at least one digital-to-analog converter to the at least one connector, and a second output path from the at least one digital-to-analog converter to the at least one connector. A method of generating a analog signal includes generating at least one analog signal from at least one digital-to-analog converter, transmitting a first analog signal of the at least one analog signal along a first output path from the at least one digital-to-analog converter to at least one connector, and transmitting a second analog signal of the at least one analog signal along a second output path from the at least one digital-to-analog converter to the at least one connector.
Abstract:
A test and measurement system including a plurality of channels and one or more processors. The one or more processors are configured to cause the test and measurement system to receive, via a first channel of the plurality of channels, a positive side of a reference differential signal pair, receive, via a second channel of the plurality of channels, a negative side of the reference differential signal pair, and produce a reference signal based the reference differential signal pair. A combined signal is received, from a combiner, that is a balanced signal produced from the reference differential signal pair. A de-embed filter is generated based on the reference signal and the combined signal and an additional signal is received from the combiner and an effect of the combiner is removed from the additional signal by applying the de-embed filter to the additional signal.
Abstract:
A machine-implemented method can include receiving a common input signal over M parallel time-interleaved (TI) analog to digital converter (ADC) channels, determining a multiple-input, multiple-output finite impulse response (FIR) filter structure for correcting bandwidth mismatches between the M parallel TIADC channels, and providing a common output signal comprising TI data corresponding to the M parallel TIADC corrected channels.
Abstract:
A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.
Abstract:
Systems and methods directed towards reducing noise introduced into a signal when processing the signal are discussed herein. In embodiments a signal may initially be split by a multiplexer into two or more frequency bands. Each of the frequency bands can then be forwarded through an assigned channel. One or more channels may include an amplifier to independently boost the signal band assigned to that channel prior to a noise source within the assigned channel. This results in boosting the signal band relative to noise introduced by the noise source. In some embodiments, a filter may also be implemented in one or more of the channels to remove noise from the channel that is outside the bandwidth of the signal band assigned to that channel. Additional embodiments may be described and/or claimed herein.
Abstract:
A continuously or step variable passive noise filter for removing noise from a signal received from a DUT added by a test and measurement instrument channel. The noise filter may include, for example, a splitter splits a signal into at least a first split signal and a second split signal. A first path receives the first split signal and includes a variable attenuator and/or a variable delay line which may be set based on the channel response of the DUT which is connected. The variable attenuator and/or the variable delay line may be continuously or stepped variable, as will be discussed in more detail below. A second path is also included to receive the second split signal and a combiner combines a signal from the first path and a signal from the second path into a combined signal.
Abstract:
Systems and methods directed towards reducing noise introduced into a signal when processing the signal are discussed herein. In embodiments a signal may initially be split by a multiplexer into two or more frequency bands. Each of the frequency bands can then be forwarded through an assigned channel. One or more channels may include an amplifier to independently boost the signal band assigned to that channel prior to a noise source within the assigned channel. This results in boosting the signal band relative to noise introduced by the noise source. In some embodiments, a filter may also be implemented in one or more of the channels to remove noise from the channel that is outside the bandwidth of the signal band assigned to that channel. Additional embodiments may be described and/or claimed herein.
Abstract:
A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.
Abstract:
A mechanism is included for jointly determining filter coefficients for Finite Impulse Response (FIR) filters in a Linear, Memory-less Non-linear (LNL), Linear compensator. Calibration signals are applied to a signal converter input in a test and measurement system. Non-linear signal components are determined in signal output from the signal converter. Non-linear filter components are determined at the LNL compensator based on the calibration signals. The non-linear signal components are then compared to the non-linear filter components. The comparison is then resolved to determine filter coefficients for first stage Finite Impulse Response (FIR) filters and second stage FIR filters in the LNL.
Abstract:
A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.