公开(公告)号：US20160055096A1

公开(公告)日：2016-02-25

申请号：US14931406

申请日：2015-11-03

Applicant: Texas Instruments Incorporated

Inventor： Kai Chirca ,  Matthew D Pierson ,  Daniel B Wu ,  Timothy D Anderson

IPC: G06F12/10 ,  G06F13/40 ,  G06F13/28 ,  G06F12/08

CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.

Abstract translation: 本发明结合了多核共享存储器控制器和异步协议转换桥以创建非常有效的异构多处理器系统。 在通过协议转换网桥之后，命令行进通过常规处理器端口。 这允许互连保持不变，同时连接不同处理器的任何组合。 本发明将所有处理器紧密地集成到相同的存储器控​​制器/互连中。

公开(公告)号：US09152586B2

公开(公告)日：2015-10-06

申请号：US14056775

申请日：2013-10-17

Applicant: Texas Instruments Incorporated

Inventor： Daniel B Wu ,  Matthew D Pierson ,  Kai Chirca ,  Timothy D Anderson

IPC: G06F13/16 ,  G06F13/40 ,  G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

Abstract translation: 为了能够有效跟踪事务，使用确认期望信号来给缓存一致互连提供一个交易是否需要连贯的所有权跟踪的提示。 该信号通知高速缓存相干互连，以便在读/写传输完成时期望来自发起主机的所有权转移确认信号。 因此，高速缓存相干互连可以在其一致性点继续跟踪事务，直到在必要时从发起主机接收到确认。

公开(公告)号：US09489307B2

公开(公告)日：2016-11-08

申请号：US14031390

申请日：2013-09-19

Applicant: Texas Instruments Incorporated

Inventor： Daniel B Wu ,  Timothy D Anderson

IPC: G06F13/40 ,  G06F12/08 ,  G06F13/16

CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The powerdown mechanism is isolated to just the asynchronous bridge implemented between the master and the interconnect with a basic request/acknowledge handshake between the master subsystem and the asynchronous bridge.

Abstract translation: 在高速缓存一致主机和相干系统互连之间实现异步双域网桥。 该桥具有两个半部分，每个时钟/电源下降域主和互连中一个。 掉电机制与主站和互连之间实现的异步桥隔离，主站与异步桥之间的基本请求/确认握手。

公开(公告)号：US09304954B2

公开(公告)日：2016-04-05

申请号：US14031567

申请日：2013-09-19

Applicant: Texas Instruments Incorporated

Inventor： Daniel B Wu ,  Matthew D Pierson ,  Kai Chirca

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/40 ,  G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The asynchronous bridge is aware of the endian view used by each individual processor within the attached subsystem, and can perform the appropriate endian conversion on each processor's transactions to adapt the transaction to/from the endian view used by the interconnect.

Abstract translation: 在高速缓存一致主机和相干系统互连之间实现异步双域网桥。 该桥具有两个半部分，每个时钟/电源下降域主和互连中一个。 异步网桥了解连接子系统内每个处理器使用的端点视图，并且可以对每个处理器的事务执行适当的端序转换，以使交易与互连使用的端点视图相适应。

公开(公告)号：US09372808B2

公开(公告)日：2016-06-21

申请号：US14059732

申请日：2013-10-22

Applicant: Texas Instruments Incorporated

Inventor： Matthew D Pierson ,  Daniel B Wu ,  Kai Chirca

IPC: G06F12/08 ,  G06F12/10 ,  G06F13/16 ,  H04L29/06 ,  G06F13/42 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: This invention mitigates these deadlocking issues by a adding a separate non-blocking pipeline for snoop returns. This separate pipeline would not be blocked behind coherent requests. This invention also repartitions the master initiated traffic to move cache evictions (both with and without data) and non-coherent writes to the new non-blocking channel. This non-blocking pipeline removes the need for any coherent requests to complete before the snoop request can reach the memory controller. Repartitioning cache initiated evictions to the non-blocking pipeline prevents deadlock when snoop and eviction occur concurrently. The non-blocking channel of this invention combines snoop responses from memory controller initiated requests and master initiated evictions/non-coherent writes.

Abstract translation: 本发明通过为窥探返回添加单独的非阻塞管道来缓解这些死锁问题。 这个单独的管道不会被阻塞在一致的请求之后。 本发明还重新分配主发起的流量以移动高速缓存驱逐（包括和不具有数据）和非相干写入到新的非阻塞信道。 这种非阻塞管道消除了在侦听请求到达内存控制器之前需要完成的任何一致的请求。 重新分区高速缓存启动的撤回到非阻塞管道可以同时发生侦听和撤离时防止死锁。 本发明的非阻塞信道组合来自存储器控制器发起的请求和主发起的驱逐/非相干写入的窥探响应。

公开(公告)号：US09372799B2

公开(公告)日：2016-06-21

申请号：US14841956

申请日：2015-09-01

Applicant: Texas Instruments Incorporated

Inventor： Daniel B Wu ,  Matthew D Pierson ,  Kai Chirca ,  Timothy D Anderson

IPC: G06F13/00 ,  G06F12/08 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

公开(公告)号：US20140115266A1

公开(公告)日：2014-04-24

申请号：US14056775

申请日：2013-10-17

Applicant: Texas Instruments Incorporated

Inventor： Daniel B Wu ,  Matthew D Pierson ,  Kai Chirca ,  Timothy D Anderson

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

Abstract translation: 为了能够有效跟踪事务，使用确认期望信号来给缓存一致互连提供一个交易是否需要连贯的所有权跟踪的提示。 该信号通知高速缓存相干互连，以便在读/写传输完成时期望来自发起主机的所有权转移确认信号。 因此，高速缓存相干互连可以在其一致性点继续跟踪事务，直到在必要时从发起主机接收到确认。

公开(公告)号：US09465767B2

公开(公告)日：2016-10-11

申请号：US14931406

申请日：2015-11-03

Applicant: Texas Instruments Incorporated

Inventor： Kai Chirca ,  Matthew D Pierson ,  Daniel B Wu ,  Timothy D Anderson

IPC: G06F15/00 ,  G06F13/42 ,  G06F12/08 ,  G06F13/16 ,  H04L29/06 ,  G06F1/12

CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.

公开(公告)号：US09465742B2

公开(公告)日：2016-10-11

申请号：US14056798

申请日：2013-10-17

Applicant: Texas Instruments Incorporated

Inventor： Daniel B Wu ,  Kai Chirca

IPC: G06F13/36 ,  G06F12/08 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

Abstract: The barrier-aware bridge tracks all outstanding transactions from the attached master. When a barrier transaction is sent from the master, it is tracked by the bridge, along with a snapshot of the current list of outstanding transactions, in a separate barrier tracking FIFO. Each barrier is separately tracked with whatever transactions that are outstanding at that time. As outstanding transaction responses are sent back to the master, their tracking information is simultaneously cleared from every barrier FIFO entry.

Abstract translation: 障碍感知桥跟踪所附主机的所有未完成交易。 当从主机发送屏障事务时，它将在单独的屏障跟踪FIFO中由桥跟踪，以及当前未完成事务列表的快照。 每个屏障都被单独跟踪，当时任何未完成的交易。 由于未完成的交易响应被发送回主机，它们的跟踪信息将同时从每个障碍FIFO条目中清除。

公开(公告)号：US09465741B2

公开(公告)日：2016-10-11

申请号：US14056729

申请日：2013-10-17

Applicant: Texas Instruments Incorporated

Inventor： Kai Chirca ,  Daniel B Wu ,  Matthew D Pierson ,  Timothy D. Anderson

IPC: G06F13/40 ,  G06F12/08 ,  G06F13/16

CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The asynchronous bridge is aware of the bus protocols used by each individual processor within the attached subsystem, and can perform the appropriate protocol conversion on each processor's transactions to adapt the transaction to/from the bus protocol used by the interconnect.

Abstract translation: 在高速缓存一致主机和相干系统互连之间实现异步双域网桥。 该桥具有两个半部分，每个时钟/电源下降域主和互连中一个。 异步网桥了解连接子系统内每个处理器所使用的总线协议，并且可以对每个处理器的事务执行适当的协议转换，以使交易与互连使用的总线协议相适应。