公开(公告)号：US20240361699A1

公开(公告)日：2024-10-31

申请号：US18308901

申请日：2023-04-28

Applicant: Texas Instruments Incorporated

Inventor： Yunlong Liu ,  Hong Yang ,  Peng Li ,  Yung Shan Chang ,  Sheng Pin Yang ,  Ya Ping Chen

IPC: G03F7/22 ,  G01B5/06 ,  G01B11/06

CPC classification number: G03F7/22 ,  G01B5/06 ,  G01B11/06 ,  G03F7/039

Abstract: A method of forming a microelectronic device includes forming positive tone photoresist on the microelectronic device, filling a trench, extending over a top surface adjacent to the trench, and covering a thickness monitor on a substrate containing the microelectronic device. The photoresist in and over the trench is exposed at a trench energy dose, and the photoresist in the monitor area is exposed at a monitor energy dose that is less than the trench energy dose. The photoresist is developed, leaving photoresist in the trench having an in-trench thickness less than the depth of the trench and leaving an in-monitor thickness of the photoresist on the monitor area less than an unexposed thickness. The in-monitor thickness of the photoresist on the monitor area may be measured and the measured thickness value may be used with a calibration chart to estimate the in-trench thickness of the photoresist.

公开(公告)号：US20240429290A1

公开(公告)日：2024-12-26

申请号：US18751877

申请日：2024-06-24

Applicant: Texas Instruments Incorporated

Inventor： Ya Ping Chen ,  Yunlong Liu ,  Hong Yang ,  Jing Hu ,  Chao Zhuang ,  Peng Li ,  Sheng Pin Yang

IPC: H01L29/40 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device includes etching a first trench and a second trench in an epitaxial layer over a semiconductor and forming a dielectric liner within the trenches. A photoresist layer is formed within the trenches and over the epitaxial layer and given a post-exposure bake at a first temperature. The photoresist layer is then given an adhesion-promoting bake at a greater second temperature; The photoresist layer is then removed from a top portion the trenches, thereby exposing a top portion of the dielectric liner and leaving a remaining portion of the photoresist in a bottom portion of the trenches. The exposed dielectric liner is etched, thereby leaving a remaining portion of the dielectric liner in the top portion of the trenches. The remaining portion of the photoresist is removed and the trenches are filled with a polysilicon layer.

公开(公告)号：US09006809B2

公开(公告)日：2015-04-14

申请号：US14280911

申请日：2014-05-19

Applicant: Texas Instruments Incorporated

Inventor： Fei Xie ,  Wen Cheng Tien ,  Ya Ping Chen ,  Li Bin Man ,  Kuo Jung Chen ,  Yu Liu ,  Tian Yi Zhang ,  Sisi Xie

IPC: H01L27/108 ,  H01L29/94 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L29/7827 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823475 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7811 ,  Y02P80/30

Abstract: A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a second opening over a gate stack in a second die area having the top dielectric, a hard mask, and a gate electrode. The top dielectric layer is etched to form a semiconductor contact while etching at least a portion the hard mask layer thickness over a gate contact area exposed by the second opening. An inter-layer dielectric (ILD) is deposited. A photosensitive material is patterned to generate a third opening in the photosensitive material over the semiconductor contact and a fourth opening inside the gate contact area. The ILD is etched through to reopen the semiconductor contact while etching through the ILD and residual hard mask if present to provide a gate contact to the gate electrode.

Abstract translation: 一种接触MOS器件的方法。 感光材料中的第一开口形成在具有第一管芯区域中的顶部电介质的衬底上，并且在具有顶部电介质的第二管芯区域中的栅极堆叠上的第二开口，硬掩模和栅极电极。 蚀刻顶部电介质层以形成半导体接触，同时在由第二开口暴露的栅极接触区域上蚀刻至少一部分硬掩模层厚度。 沉积层间电介质（ILD）。 图案化感光材料以在半导体触点上方的感光材料中产生第三开口，并在栅极接触区域内产生第四开口。 蚀刻通过ILD以重新打开半导体接触，同时蚀刻通过ILD和残余硬掩模（如果存在）以提供与栅电极的栅极接触。

公开(公告)号：US11658241B2

公开(公告)日：2023-05-23

申请号：US16237210

申请日：2018-12-31

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Hong Yang ,  Ya Ping Chen ,  Thomas Eugene Grebs

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/872 ,  H01L21/8234 ,  H01L29/40

CPC classification number: H01L29/7827 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/872

Abstract: An integrated circuit includes a trench gate MOSFET including MOSFET cells. Each MOSFET cell includes an active trench gate in an n-epitaxial layer oriented in a first direction with a polysilicon gate over a lower polysilicon portion. P-type body regions are between trench gates and are separated by an n-epitaxial region. N-type source regions are located over the p-type regions. A gate dielectric layer is between the polysilicon gates and the body regions. A metal-containing layer contacts the n-epitaxial region to provide an anode of an embedded Schottky diode. A dielectric layer over the n-epitaxial layer has metal contacts therethrough connecting to the n-type source regions, to the p-type body regions, and to the anode of the Schottky diode.

公开(公告)号：US11127852B2

公开(公告)日：2021-09-21

申请号：US16233643

申请日：2018-12-27

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Hong Yang ,  Ya Ping Chen ,  Yunlong Liu ,  Fei Ma

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L21/225 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08

Abstract: A trench gate metal oxide semiconductor field effect transistor (MOSFET) device includes an epitaxial layer on a substrate both doped a first conductivity type. Active area trenches have polysilicon gates over a double shield field plate. A junction termination trench includes a single shield field plate in a junction termination area which encloses the active area that includes a retrograde dopant profile of the second conductivity type into the epitaxial layer in the junction termination area. Pbody regions of a second conductivity type are between active trenches and between the outermost active trench and the junction termination trench. Source regions of the first conductivity type are in the body regions between adjacent active trenches. Metal contacts are over contact apertures that extend through a pre-metal dielectric layer reaching the body region under the source region, the single shield field plate, and that couples together the polysilicon gates.