公开(公告)号：US11658241B2

公开(公告)日：2023-05-23

申请号：US16237210

申请日：2018-12-31

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Hong Yang ,  Ya Ping Chen ,  Thomas Eugene Grebs

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/872 ,  H01L21/8234 ,  H01L29/40

CPC classification number: H01L29/7827 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/872

Abstract: An integrated circuit includes a trench gate MOSFET including MOSFET cells. Each MOSFET cell includes an active trench gate in an n-epitaxial layer oriented in a first direction with a polysilicon gate over a lower polysilicon portion. P-type body regions are between trench gates and are separated by an n-epitaxial region. N-type source regions are located over the p-type regions. A gate dielectric layer is between the polysilicon gates and the body regions. A metal-containing layer contacts the n-epitaxial region to provide an anode of an embedded Schottky diode. A dielectric layer over the n-epitaxial layer has metal contacts therethrough connecting to the n-type source regions, to the p-type body regions, and to the anode of the Schottky diode.

公开(公告)号：US20190385992A1

公开(公告)日：2019-12-19

申请号：US16546475

申请日：2019-08-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Osvaldo Jorge Lopez ,  Walter Hans Paul Schroen ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/16 ,  H01L25/18 ,  H01L23/00 ,  H01L21/50 ,  H01L23/14 ,  H01L23/13 ,  H01L23/06 ,  H01L23/053 ,  H01L29/06 ,  H01L25/00 ,  H01L31/02 ,  H01L31/18 ,  H01L27/088 ,  H01L27/082 ,  H01L31/0216 ,  H01L31/042 ,  H01L31/028

Abstract: A self-powered electronic system comprises a first chip of single-crystalline semiconductor embedded in a second chip of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container bordered by ridges. The flat side of the slab includes a heavily n-doped region forming a pn-junction with the p-type bulk. A metal-filled deep silicon via through the p-type ridge connects the n-region with the terminal on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

公开(公告)号：US10438936B2

公开(公告)日：2019-10-08

申请号：US15820246

申请日：2017-11-21

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Walter Hans Paul Schroen ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/16 ,  H01L31/028 ,  H01L31/042 ,  H01L31/0216 ,  H01L27/082 ,  H01L27/088 ,  H01L31/18 ,  H01L31/02 ,  H01L25/00 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/14 ,  H01L21/50 ,  H01L23/00 ,  H01L25/18 ,  H01L29/06 ,  H01L23/498

Abstract: A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

公开(公告)号：US20170194306A1

公开(公告)日：2017-07-06

申请号：US15465455

申请日：2017-03-21

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Walter Hans Paul Schroen ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/16 ,  H01L31/0216 ,  H01L31/028 ,  H01L25/00 ,  H01L31/18 ,  H01L27/082 ,  H01L27/088 ,  H01L31/02 ,  H01L31/042

CPC classification number: H01L25/167 ,  H01L21/50 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49844 ,  H01L24/83 ,  H01L25/18 ,  H01L25/50 ,  H01L27/082 ,  H01L27/088 ,  H01L29/0657 ,  H01L31/02008 ,  H01L31/02168 ,  H01L31/028 ,  H01L31/042 ,  H01L31/1804 ,  H01L31/1868 ,  H01L2224/83851 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/04642 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10155 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/1427 ,  H01L2924/15

Abstract: A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

公开(公告)号：US09318598B2

公开(公告)日：2016-04-19

申请号：US14291913

申请日：2014-05-30

Applicant: Texas Instruments Incorporated

Inventor： Thomas Eugene Grebs ,  Touhidur Rahman ,  Christopher Boguslaw Kocon

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49 ,  H01L29/40 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/7813 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/861

Abstract: A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the semiconductor layer. The transistor cells include a first cell type including a first trench providing a first gate electrode or the first gate electrode is on the semiconductor surface between the first trench and a second trench, and a first source region is formed in the body region. The first gate electrode is electrically isolated from the first source region. A second cell type has a third trench providing a second gate electrode or the second gate electrode is on the semiconductor surface between the third trench and a fourth trench, and a second source region is in the body region. An electrically conductive member directly connects the second gate electrode, first source region and second source region together.

公开(公告)号：US11177246B2

公开(公告)日：2021-11-16

申请号：US16546475

申请日：2019-08-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Osvaldo Jorge Lopez ,  Walter Hans Paul Schroen ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/16 ,  H01L31/028 ,  H01L31/042 ,  H01L31/0216 ,  H01L27/082 ,  H01L27/088 ,  H01L31/18 ,  H01L31/02 ,  H01L25/00 ,  H01L29/06 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/14 ,  H01L21/50 ,  H01L23/00 ,  H01L25/18 ,  H01L25/04 ,  H01L23/498

Abstract: A self-powered electronic system comprises a first chip of single-crystalline semiconductor embedded in a second chip of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container bordered by ridges. The flat side of the slab includes a heavily n-doped region forming a pn-junction with the p-type bulk. A metal-filled deep silicon via through the p-type ridge connects the n-region with the terminal on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

公开(公告)号：US09859261B2

公开(公告)日：2018-01-02

申请号：US15465455

申请日：2017-03-21

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Walter Hans Paul Schroen ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/16 ,  H01L31/02 ,  H01L31/0216 ,  H01L31/028 ,  H01L31/042 ,  H01L31/18 ,  H01L27/082 ,  H01L27/088 ,  H01L25/00

CPC classification number: H01L25/167 ,  H01L21/50 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49844 ,  H01L24/83 ,  H01L25/18 ,  H01L25/50 ,  H01L27/082 ,  H01L27/088 ,  H01L29/0657 ,  H01L31/02008 ,  H01L31/02168 ,  H01L31/028 ,  H01L31/042 ,  H01L31/1804 ,  H01L31/1868 ,  H01L2224/83851 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/04642 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10155 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/1427 ,  H01L2924/15

Abstract: A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

公开(公告)号：US09818662B2

公开(公告)日：2017-11-14

申请号：US14702031

申请日：2015-05-01

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L23/14 ,  H01L23/13 ,  H01L21/50 ,  H01L21/98 ,  H01L21/52 ,  H01L25/16 ,  H01L21/48 ,  H01L25/00 ,  H01L21/78

CPC classification number: H01L23/147 ,  H01L21/481 ,  H01L21/78 ,  H01L23/057 ,  H01L23/08 ,  H01L23/13 ,  H01L25/16 ,  H01L25/165 ,  H01L25/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A packaged electronic system comprises a slab (210) of low-grade silicon (l-g-Si) configured as ridges (114) framing a depression of depth (112) including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals (209b) connected to attachment pads in the central area; and semiconductor chips (120, 130) having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.

公开(公告)号：US09583611B2

公开(公告)日：2017-02-28

申请号：US15069038

申请日：2016-03-14

Applicant: Texas Instruments Incorporated

Inventor： Thomas Eugene Grebs ,  Touhidur Rahman ,  Christopher Boguslaw Kocon

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49 ,  H01L29/40 ,  H01L29/66 ,  H01L29/739 ,  H01L29/08 ,  H01L29/417 ,  H01L29/861

CPC classification number: H01L29/7813 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/861

Abstract: A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the semiconductor layer. The transistor cells include a first cell type including a first trench providing a first gate electrode or the first gate electrode is on the semiconductor surface between the first trench and a second trench, and a first source region is formed in the body region. The first gate electrode is electrically isolated from the first source region. A second cell type has a third trench providing a second gate electrode or the second gate electrode is on the semiconductor surface between the third trench and a fourth trench, and a second source region is in the body region. An electrically conductive member directly connects the second gate electrode, first source region and second source region together.

Abstract translation: 沟槽MOSFET器件包括第一掺杂类型的半导体层。 MOS晶体管单元处于半导体层中的第二掺杂类型的体区。 晶体管单元包括第一单元类型，包括提供第一栅电极的第一沟槽或者第一栅电极位于第一沟槽和第二沟槽之间的半导体表面上，并且第一源区形成在体区中。 第一栅电极与第一源区电隔离。 第二单元类型具有提供第二栅电极的第三沟槽，或者第二栅极位于第三沟槽和第四沟槽之间的半导体表面上，第二源极区在体区中。 导电构件将第二栅极电极，第一源极区域和第二源极区域直接连接在一起。

公开(公告)号：US20160172338A1

公开(公告)日：2016-06-16

申请号：US15053089

申请日：2016-02-25

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/50 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49844 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/074 ,  H01L25/18 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/06181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/83851 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/00 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/04642 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10155 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1037 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/1427 ,  H01L2924/15156 ,  H01L2924/157 ,  H01L2224/83

Abstract: An electronic system comprises a first chip of single-crystalline semiconductor shaped as a hexahedron and including a first electronic device embedded in a second chip of single-crystalline semiconductor shaped as a container having a slab bordered by retaining walls, and including a second electronic device. The container shaped as a slab bordered by the retaining walls and including conductive traces and terminals. The first chip is attached to the slab of second chip, forming nested chips. The first and second chips embedded in the container. The nested first and second chips are operable as an electronic system and the container is operable as the package of the system.

Abstract translation: 电子系统包括形成为六面体的单晶半导体的第一芯片，并且包括第一电子器件，所述第一电子器件嵌入在形成为容器的单晶半导体的第二芯片中，所述第一芯片具有由保持壁邻接的板，并且包括第二电子器件 。 容器形成为由挡土墙毗邻并包括导电迹线和端子的平板。 第一芯片连接到第二芯片的板上，形成嵌套芯片。 第一个和第二个芯片嵌入容器。 嵌套的第一和第二芯片可操作为电子系统，并且容器可操作为系统的封装。