公开(公告)号：US20090185411A1

公开(公告)日：2009-07-23

申请号：US12017581

申请日：2008-01-22

申请人： Thomas Happ ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Bipin Rajendran ,  Min Yang

发明人： Thomas Happ ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Bipin Rajendran ,  Min Yang

IPC分类号： G11C11/00 ,  H01L21/06

CPC分类号： H01L27/24 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/71 ,  G11C2213/72

摘要： The integrated circuit includes a first metal line and a first diode coupled to the first metal line. The integrated circuit includes a first resistivity changing material coupled to the first diode and a second metal line coupled to the first resistivity changing material.

摘要翻译： 集成电路包括耦合到第一金属线的第一金属线和第一二极管。 集成电路包括耦合到第一二极管的第一电阻率变化材料和耦合到第一电阻率变化材料的第二金属线。

公开(公告)号：US08586960B2

公开(公告)日：2013-11-19

申请号：US12142239

申请日：2008-06-19

申请人： Thomas Happ ,  Hsiang-Lan Lung ,  Bipin Rajendran ,  Min Yang

发明人： Thomas Happ ,  Hsiang-Lan Lung ,  Bipin Rajendran ,  Min Yang

IPC分类号： H01L29/06

CPC分类号： H01L27/2481 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.

公开(公告)号：US20090200534A1

公开(公告)日：2009-08-13

申请号：US12027675

申请日：2008-02-07

申请人： Bipin Rajendran ,  Thomas Happ ,  Hsiang-Lan Lung ,  Min Yang

发明人： Bipin Rajendran ,  Thomas Happ ,  Hsiang-Lan Lung ,  Min Yang

IPC分类号： H01L47/00 ,  H01L21/36

CPC分类号： H01L27/24 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02667 ,  H01L27/1021 ,  H01L29/8613

摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.

摘要翻译： 本发明在一个实施方案中提供了一种制备PN结的方法，所述方法至少包括提供含Si衬底的步骤; 在含Si衬底上形成绝缘层; 通过所述绝缘层形成通孔以露出所述含Si衬底的至少一部分; 形成含Si衬底的暴露部分的种子层; 在至少种子层上形成非晶态Si; 转化至少一部分非晶Si以提供晶体Si; 以及形成邻接所述晶体Si中的第二掺杂区的第一掺杂区。

公开(公告)号：US07955958B2

公开(公告)日：2011-06-07

申请号：US12027675

申请日：2008-02-07

申请人： Bipin Rajendran ,  Thomas Happ ,  Hsiang-Lan Lung ,  Min Yang

发明人： Bipin Rajendran ,  Thomas Happ ,  Hsiang-Lan Lung ,  Min Yang

IPC分类号： H01L21/20

CPC分类号： H01L27/24 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02667 ,  H01L27/1021 ,  H01L29/8613

摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.

摘要翻译： 本发明在一个实施方案中提供了一种制备PN结的方法，所述方法至少包括提供含Si衬底的步骤; 在含Si衬底上形成绝缘层; 通过所述绝缘层形成通孔以暴露所述含Si衬底的至少一部分; 形成含Si衬底的暴露部分的种子层; 在至少种子层上形成非晶态Si; 转化至少一部分非晶Si以提供晶体Si; 以及形成邻接所述晶体Si中的第二掺杂区的第一掺杂区。

公开(公告)号：US20090316473A1

公开(公告)日：2009-12-24

申请号：US12142239

申请日：2008-06-19

申请人： Thomas Happ ,  Hsiang-Lan Lung ,  Bipin Rajendran ,  Min Yang

发明人： Thomas Happ ,  Hsiang-Lan Lung ,  Bipin Rajendran ,  Min Yang

IPC分类号： G11C11/00 ,  H01L47/00 ,  H01L21/425

CPC分类号： H01L27/2481 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.

摘要翻译： 集成电路包括包括隔离区域的衬底，在隔离区域之间的衬底中形成的第一导电线和形成在衬底中的垂直二极管。 集成电路包括耦合到垂直二极管的触点和耦合到触点的存储元件。 第一导线提供垂直二极管的一部分。

公开(公告)号：US08637844B2

公开(公告)日：2014-01-28

申请号：US13097307

申请日：2011-04-29

申请人： Bipin Rajendran ,  Thomas Happ ,  Hsiang-Lan Lung ,  Min Yang

发明人： Bipin Rajendran ,  Thomas Happ ,  Hsiang-Lan Lung ,  Min Yang

IPC分类号： H01L47/00

CPC分类号： H01L27/24 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02667 ,  H01L27/1021 ,  H01L29/8613

摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.

摘要翻译： 本发明在一个实施方案中提供了一种制备PN结的方法，所述方法至少包括提供含Si衬底的步骤; 在含Si衬底上形成绝缘层; 通过所述绝缘层形成通孔以露出所述含Si衬底的至少一部分; 形成含Si衬底的暴露部分的种子层; 在至少种子层上形成非晶态Si; 转化至少一部分非晶Si以提供晶体Si; 以及形成邻接所述晶体Si中的第二掺杂区的第一掺杂区。

公开(公告)号：US20110198557A1

公开(公告)日：2011-08-18

申请号：US13097307

申请日：2011-04-29

申请人： Bipin Rajendran ,  Thomas Happ ,  Hsiang-Lan Lung ,  Min Yang

发明人： Bipin Rajendran ,  Thomas Happ ,  Hsiang-Lan Lung ,  Min Yang

IPC分类号： H01L47/00

CPC分类号： H01L27/24 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02667 ,  H01L27/1021 ,  H01L29/8613

摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.

摘要翻译： 本发明在一个实施方案中提供了一种制备PN结的方法，所述方法至少包括提供含Si衬底的步骤; 在含Si衬底上形成绝缘层; 通过所述绝缘层形成通孔以露出所述含Si衬底的至少一部分; 形成含Si衬底的暴露部分的种子层; 在至少种子层上形成非晶态Si; 转化至少一部分非晶Si以提供晶体Si; 以及形成邻接所述晶体Si中的第二掺杂区的第一掺杂区。

公开(公告)号：US20100193763A1

公开(公告)日：2010-08-05

申请号：US12727672

申请日：2010-03-19

申请人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

发明人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

IPC分类号： H01L45/00

CPC分类号： B82Y10/00 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

摘要： A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

摘要翻译： 使用具有大约10nm的尺寸的纳米颗粒层形成电流收缩层或作为用于从下面的绝​​缘体层形成电流收缩层的硬掩模。 纳米颗粒优选在下面的表面上自对准和/或自平坦化。 电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电 材料。 电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。 由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

公开(公告)号：US07745807B2

公开(公告)日：2010-06-29

申请号：US11776301

申请日：2007-07-11

申请人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

发明人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

IPC分类号： H01L29/02

CPC分类号： B82Y10/00 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

摘要： A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

摘要翻译： 使用具有大约10nm的尺寸的纳米颗粒层形成电流收缩层或作为用于从下面的绝​​缘体层形成电流收缩层的硬掩模。 纳米颗粒优选在下面的表面上自对准和/或自平坦化。 电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电 材料。 电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。 由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

公开(公告)号：US20090014704A1

公开(公告)日：2009-01-15

申请号：US11776301

申请日：2007-07-11

申请人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

发明人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

IPC分类号： H01L29/04

CPC分类号： B82Y10/00 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

摘要： A layer of nanopaiticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

摘要翻译： 使用具有大约10nm的尺寸的纳米颗粒层来形成电流收缩层或用作从底层绝缘体层形成电流收缩层的硬掩模。 纳米颗粒优选在下面的表面上自对准和/或自平坦化。 电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电 材料。 电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。 由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。