摘要:
An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.
摘要:
The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
摘要:
The integrated circuit includes a first metal line and a first diode coupled to the first metal line. The integrated circuit includes a first resistivity changing material coupled to the first diode and a second metal line coupled to the first resistivity changing material.
摘要:
The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
摘要:
An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.
摘要:
The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
摘要:
The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
摘要:
A memory array with self-centered diode access devices results from a process in which diodes are formed in the fill material, each diode having a lightly-doped first layer of the same conductivity type as the conductive lines; a heavily doped second layer of opposite conductivity type; and a conductive cap. Self-aligned, and self-centered spacers in the self-aligned vias define pores that expose the conductive cap. Memory material is deposited within the pores, the memory material making contact with the conductive cap. A top electrode is formed in contact with the memory material.
摘要:
A method of fabricating a memory array. The method begins with a structure, generally composed of dielectric fill material and having conductive lines formed at its lower portion, and a sacrificial layer formed on its upper surface. Diodes are formed in the fill material, each diode having a lightly-doped first layer of the same conductivity type as the conductive lines; a heavily doped second layer of opposite conductivity type; and a conductive cap. Self-aligned vias are formed over the diodes. Self-aligned, and self-centered spacers in the self-aligned vias define pores that expose the conductive cap. Memory material is deposited within the pores, the memory material making contact with the conductive cap. A top electrode is formed in contact with the memory material.
摘要:
Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a width less than that of the base portion. A dielectric surrounds the bottom electrode and has a top surface. A memory element is overlying the bottom electrode and includes a recess portion extending from the top surface of the dielectric to contact the pillar portion of the bottom electrode, wherein the recess portion of the memory element has a width substantially equal to the width of the pillar portion of the bottom electrode. A top electrode is on the memory element.