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公开(公告)号：US09437257B2
公开(公告)日：2016-09-06
申请号：US13765513
申请日：2013-02-12
申请人： Tien-Chun Yang , Yue-Der Chih , Chan-Hong Chern , Tao Wen Chung
发明人： Tien-Chun Yang , Yue-Der Chih , Chan-Hong Chern , Tao Wen Chung
CPC分类号： G11C7/062 , G11C7/14 , G11C13/004 , G11C2207/063
摘要： A sensing circuit includes a sensing resistor, a reference resistor and a comparator. The comparator has a first input coupled to the sensing resistor, a second input coupled to the reference resistor, and an output. The first input is configured to be coupled to a data bit line associated with a memory cell to receive a sensing input voltage caused by a cell current of the memory cell flowing through the sensing resistor. The second input is configured to be coupled to a reference bit line associated with a reference cell to receive a sensing reference voltage caused by a reference current of the reference cell flowing through the reference resistor. The comparator is configured to generate, at the output, an output signal indicating a logic state of data stored in the memory cell based on a comparison between the sensing input voltage and the sensing reference voltage.
摘要翻译： 感测电路包括感测电阻器，参考电阻器和比较器。 比较器具有耦合到感测电阻器的第一输入端，耦合到参考电阻器的第二输入端和输出端。 第一输入被配置为耦合到与存储器单元相关联的数据位线，以接收由流过感测电阻器的存储单元的单元电流引起的感测输入电压。 第二输入被配置为耦合到与参考单元相关联的参考位线，以接收由参考电池流过参考电阻器的参考电流引起的感测参考电压。 比较器被配置为基于感测输入电压和感测参考电压之间的比较，在输出处产生指示存储在存储器单元中的数据的逻辑状态的输出信号。
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公开(公告)号：US08575966B2
公开(公告)日：2013-11-05
申请号：US13718235
申请日：2012-12-18
摘要： A method of operating a charge pump of a phase-lock assistant circuit includes determining a first relative timing relationship of a phase of a data signal to a phase of a first phase clock. A second relative timing relationship of the phase of the data signal to a phase of a second phase clock is determined, and the first and second phase clocks have a 45° phase difference. An up signal and a down signal are generated in response to the first relative timing relationship and the second relative timing relationship. The charge pump circuit is driven according to the up signal and the down signal.
摘要翻译： 操作锁相辅助电路的电荷泵的方法包括确定数据信号的相位与第一相位时钟的相位的第一相对定时关系。 确定数据信号的相位与第二相位时钟的相位的第二相对定时关系，并且第一和第二相位时钟具有45°的相位差。 响应于第一相对定时关系和第二相对定时关系产生升高信号和下降信号。 电荷泵电路根据上升信号和下降信号进行驱动。
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公开(公告)号：US20110199154A1
公开(公告)日：2011-08-18
申请号：US12704719
申请日：2010-02-12
申请人： Chiang Pu , Ming-Chich Huang , Chan-Hong Chern , Tien-Chun Yang
发明人： Chiang Pu , Ming-Chich Huang , Chan-Hong Chern , Tien-Chun Yang
IPC分类号： G05F1/10
CPC分类号： G01C19/5776
摘要： Some embodiments regard a circuit comprising: a high voltage transistor providing a resistance; an amplifier configured to receive a current and to convert the current to a first voltage that is used in a loop creating the current; and an automatic level control circuit that, based on an AC amplitude of the first voltage, adjusts a second voltage at a gate of the high voltage transistor and thereby adjusts the resistance and the first voltage; wherein the automatic level control circuit is configured to adjust the first voltage toward the first reference voltage if the first voltage differs from a first reference voltage.
摘要翻译： 一些实施例涉及一种电路，包括：提供电阻的高压晶体管; 放大器，被配置为接收电流并将电流转换成在产生电流的环路中使用的第一电压; 以及自动电平控制电路，其基于所述第一电压的交流振幅调整所述高电压晶体管的栅极处的第二电压，从而调整所述电阻和所述第一电压; 其中所述自动电平控制电路被配置为如果所述第一电压与第一参考电压不同，则将所述第一电压调整为朝向所述第一参考电压。
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4.发明授权Integrated circuits including a charge pump circuit and operating methods thereof 有权包括电荷泵电路的集成电路及其操作方法公开(公告)号：US08183913B2
公开(公告)日：2012-05-22
申请号：US12706886
申请日：2010-02-17
CPC分类号： G05F1/10 , G05F3/02 , H03L7/0895 , H03L7/0896 , H03L7/0898
摘要： An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.
摘要翻译： 集成电路包括第一电流源。 第二电流源经由导线与第一电流源电耦合。 开关电路耦合在第一电流源和第二电流源之间。 第一电路耦合在第一节点和第二节点之间。 第一节点设置在第一电流源和开关电路之间。 第二节点与第一电流源耦合。 第一电路被配置为基本上均衡第一节点和第二节点上的电压。 第二电路耦合在第三节点和第四节点之间。 第三节点设置在第二电流源和开关电路之间。 第四节点被布置成与第二电流源耦合。 第二电路被配置为基本上均衡第三节点和第四节点上的电压。
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5.发明授权公开(公告)号：US07961050B1
公开(公告)日：2011-06-14
申请号：US12706872
申请日：2010-02-17
IPC分类号： H03F3/04
CPC分类号： H03F3/45197 , H03F3/45183 , H03F3/45192 , H03F2203/45292 , H03F2203/45458 , H03F2203/45496 , H03F2203/45562 , H03F2203/45631 , H03F2203/45644 , H03F2203/45686 , H03F2203/45702
摘要： An integrated circuit includes a differential amplifier. The differential amplifier includes at least one output end. A circuit is coupled with the at least one output end of the differential amplifier. The circuit does not include a resistor-capacitor (RC) network and is configured for providing a negative impedance to the differential amplifier for adjusting a direct current (DC) gain of the integrated circuit.
摘要翻译： 集成电路包括差分放大器。 差分放大器包括至少一个输出端。 电路与差分放大器的至少一个输出端耦合。 该电路不包括电阻 - 电容（RC）网络，并被配置为向差分放大器提供负阻抗以调整集成电路的直流（DC）增益。
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公开(公告)号：US08324960B2
公开(公告)日：2012-12-04
申请号：US12849503
申请日：2010-08-03
CPC分类号： H02M3/07
摘要： An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is configured to receive a voltage input to generate the voltage output having a maximum voltage higher than the voltage input. The gate oxide layer thickness of the MOS capacitor is less than that of the first PMOS transistor.
摘要翻译： 集成电路包括第一PMOS晶体管，其中其漏极被布置成耦合到电压输出，并且其源极耦合到第二PMOS晶体管的漏极。 第二PMOS晶体管的源极被布置成耦合到高电源电压。 MOS电容器的源极和漏极耦合到第一PMOS晶体管的源极。 NMOS晶体管的漏极耦合到第一PMOS晶体管的漏极。 集成电路被配置为接收电压输入以产生具有高于电压输入的最大电压的电压输出。 MOS电容器的栅氧化层厚度小于第一PMOS晶体管的栅极氧化层厚度。
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公开(公告)号：US08004354B1
公开(公告)日：2011-08-23
申请号：US12704719
申请日：2010-02-12
申请人： Chiang Pu , Ming-Chich Huang , Chan-Hong Chern , Tien-Chun Yang
发明人： Chiang Pu , Ming-Chich Huang , Chan-Hong Chern , Tien-Chun Yang
IPC分类号： H03F1/36
CPC分类号： G01C19/5776
摘要： Some embodiments regard a circuit comprising: a high voltage transistor providing a resistance; an amplifier configured to receive a current and to convert the current to a first voltage that is used in a loop creating the current; and an automatic level control circuit that, based on an AC amplitude of the first voltage, adjusts a second voltage at a gate of the high voltage transistor and thereby adjusts the resistance and the first voltage; wherein the automatic level control circuit is configured to adjust the first voltage toward the first reference voltage if the first voltage differs from a first reference voltage.
摘要翻译： 一些实施例涉及一种电路，包括：提供电阻的高压晶体管; 放大器，被配置为接收电流并将电流转换成在产生电流的环路中使用的第一电压; 以及自动电平控制电路，其基于所述第一电压的交流振幅调整所述高电压晶体管的栅极处的第二电压，从而调整所述电阻和所述第一电压; 其中所述自动电平控制电路被配置为如果所述第一电压与第一参考电压不同，则将所述第一电压调整为朝向所述第一参考电压。
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公开(公告)号：US08354862B2
公开(公告)日：2013-01-15
申请号：US13448878
申请日：2012-04-17
IPC分类号： H03D13/00
摘要： A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.
摘要翻译： 包括被配置为接收输入信号和时钟的第一，第三和第五相位时钟并且产生指示时钟的第一早期信号的第一电路的电路早于输入信号，并且指示时钟的第一晚信号晚于 输入信号。 电路还包括配置成接收时钟的输入信号和第二，第四和第六相位时钟的第二电路，并且产生指示时钟早于输入信号的第二早期信号，并且指示时钟的第二延迟信号是 晚于输入信号。 电路还包括被配置为产生第一增加信号的第三电路。 电路还包括被配置为产生第一减小信号的第四电路。
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公开(公告)号：US08179162B2
公开(公告)日：2012-05-15
申请号：US12835130
申请日：2010-07-13
摘要： Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.
摘要翻译： 一些实施例涉及一种电路，包括：第一电路，其被配置为将输出时钟的频率锁定到参考时钟的频率; 第二电路，被配置为将输入信号与所述输出时钟的相位时钟对准; 第三电路，被配置为使用所述输出时钟的第一组相位时钟和所述输出时钟的第二组相位时钟，以改善所述输入信号与所述输出时钟的相位时钟的对准; 以及锁定检测电路，被配置为当所述输出时钟的频率未被锁定到所述参考时钟的频率时接通所述第一电路; 并且当输出时钟的频率被锁定到参考时钟的频率时，关闭第一电路并接通第二电路和第三电路。
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公开(公告)号：US08115545B2
公开(公告)日：2012-02-14
申请号：US13177958
申请日：2011-07-07
申请人： Chiang Pu , Ming-Chieh Huang , Chan-Hong Chern , Tien-Chun Yang
发明人： Chiang Pu , Ming-Chieh Huang , Chan-Hong Chern , Tien-Chun Yang
IPC分类号： H03F1/36
CPC分类号： G01C19/5776
摘要： Some embodiments regard a circuit comprising: a high voltage transistor providing a resistance; an amplifier configured to receive a current and to convert the current to a first voltage that is used in a loop creating the current; and an automatic level control circuit that, based on an AC amplitude of the first voltage, adjusts a second voltage at a gate of the high voltage transistor and thereby adjusts the resistance and the first voltage; wherein the automatic level control circuit is configured to adjust the first voltage toward the first reference voltage if the first voltage differs from a first reference voltage.
摘要翻译： 一些实施例涉及一种电路，包括：提供电阻的高压晶体管; 放大器，被配置为接收电流并将电流转换成在产生电流的环路中使用的第一电压; 以及自动电平控制电路，其基于所述第一电压的交流振幅调整所述高电压晶体管的栅极处的第二电压，从而调整所述电阻和所述第一电压; 其中所述自动电平控制电路被配置为如果所述第一电压与第一参考电压不同，则将所述第一电压调整为朝向所述第一参考电压。
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