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    Method and semiconductor structure for implementing reach through buried interconnect for silicon-on-insulator (SOI) devices
    3.
    发明授权
    Method and semiconductor structure for implementing reach through buried interconnect for silicon-on-insulator (SOI) devices 失效
    用于通过绝缘体上硅（SOI）器件的掩埋互连实现覆盖的方法和半导体结构

    公开(公告)号：US06645796B2

    公开(公告)日：2003-11-11

    申请号：US09990477

    申请日：2001-11-21

    申请人： Todd Alan Christensen ,  John Edward Sheets, II

    发明人： Todd Alan Christensen ,  John Edward Sheets, II

    IPC分类号： H01L2100

    CPC分类号： H01L29/66772 ,  H01L27/1203 ,  H01L29/78639

    摘要： A method and semiconductor structure including silicon-on-insulator (SOI) devices are provided for implementing reach through buried interconnect. A semiconductor stack includes a predefined buried conductor to be connected through multiple insulator layers and at least one intermediate conductor above the predefined buried conductor. A hole is anisotropically etched through the semiconductor stack to the predefined buried conductor. The etched hole extends through the at least one intermediate conductor and the insulators to the predefined buried conductor in the semiconductor stack. A thin layer of insulator is deposited over an interior of the etched hole. The deposited thin insulator layer is anisotropically etched to remove the deposited thin insulator layer from a bottom of the hole exposing the predefined buried conductor in the semiconductor stack with the thin insulator layer covering sidewalls of the hole to define an insulated opening. The insulated opening is filled with an interconnect conductor to create a connection to the predefined buried conductor in the semiconductor stack. A semiconductor structure for implementing reach through buried interconnect in building semiconductors including silicon-on-insulator (SOI) devices includes the semiconductor stack. An etched hole extends through at least one intermediate conductor and the insulators to the predefined buried conductor in the semiconductor stack. A thin layer of insulator covers sidewalls of the etched hole providing an insulated opening. An interconnect conductor extending through the insulated opening is connected to the predefined buried conductor in the semiconductor stack.

    摘要翻译： 提供了一种包括绝缘体上硅（SOI）器件的方法和半导体结构，用于通过掩埋互连实现覆盖。 半导体堆叠包括要通过多个绝缘体层连接的预定掩埋导体和在预定义掩埋导体上方的至少一个中间导体。 一个孔通过半导体堆叠被各向异性地蚀刻到预定义的掩埋导体。 蚀刻孔延伸穿过至少一个中间导体和绝缘体延伸到半导体叠层中的预定掩埋导体。 绝缘体的薄层沉积在蚀刻孔的内部。 沉积的薄绝缘体层被各向异性蚀刻以从沉积在半导体堆叠中的预定掩埋导体的孔的底部去除沉积的薄绝缘体层，薄绝缘体层覆盖孔的侧壁以限定绝缘开口。 绝缘开口填充有互连导体，以形成与半导体叠层中的预定掩埋导体的连接。 用于通过包括绝缘体上硅（SOI）器件在内的建筑半导体的掩埋互连实现覆盖的半导体结构包括半导体堆叠。 蚀刻孔延伸穿过至少一个中间导体，绝缘体延伸到半导体叠层中的预定掩埋导体。 绝缘体薄层覆盖蚀刻孔的侧壁，提供绝缘开口。 延伸穿过绝缘开口的互连导体连接到半导体叠层中的预定掩埋导体。

    Implementing Decoupling Capacitors With Hot-Spot Thermal Reduction on Integrated Circuit Chips
    6.
    发明申请
    Implementing Decoupling Capacitors With Hot-Spot Thermal Reduction on Integrated Circuit Chips 失效
    在集成电路芯片上实现热点热还原实现去耦电容

    公开(公告)号：US20100032799A1

    公开(公告)日：2010-02-11

    申请号：US12186837

    申请日：2008-08-06

    申请人： Gerald Keith Bartley ,  Todd Alan Christensen ,  Paul Eric Dahlen ,  John Edward Sheets, II

    发明人： Gerald Keith Bartley ,  Todd Alan Christensen ,  Paul Eric Dahlen ,  John Edward Sheets, II

    IPC分类号： H01L29/00 ,  H01L21/20

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0805

    摘要： A method and structures are provided for implementing decoupling capacitors with hot spot thermal reduction on integrated circuit chips including silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, and an active layer carried by the thin BOX layer. A thermal conductive path is built proximate to a hotspot area in the active layer to reduce thermal effects including a backside thermal connection from a backside of the SOI structure. The backside thermal connection includes a backside etched opening extending from the backside of the SOI structure into the silicon substrate layer, a capacitor dielectric formed on said backside etched opening; and a thermal connection material deposited on said capacitor dielectric filling said backside etched opening.

    摘要翻译： 提供了一种方法和结构，用于在包括绝缘体上硅（SOI）电路的集成电路芯片上实现具有热点热还原的去耦电容器。 绝缘体上硅（SOI）结构包括硅衬底层，由硅衬底层承载的薄掩埋氧化物（BOX）层以及由薄BOX层承载的有源层。 在有源层中的热点区域附近建立导热路径，以减少热效应，包括来自SOI结构背面的背面热连接。 背面热连接包括从SOI结构的背面延伸到硅衬底层的后侧蚀刻开口，形成在所述背面蚀刻开口上的电容器电介质; 以及沉积在填充所述背面蚀刻开口的所述电容器电介质上的热连接材料。

    Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices
    7.
    发明授权
    Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices 失效
    用于实现绝缘体（SOI）器件的埋地双轨配电和集成去耦电容的方法和半导体结构

    公开(公告)号：US06492244B1

    公开(公告)日：2002-12-10

    申请号：US09990478

    申请日：2001-11-21

    申请人： Todd Alan Christensen ,  John Edward Sheets, II

    发明人： Todd Alan Christensen ,  John Edward Sheets, II

    IPC分类号： H01L2176

    CPC分类号： H01L27/1203 ,  H01L21/76243

    摘要： Methods and semiconductor structures are provided for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices. A bulk silicon substrate layer is provided that defines one power distribution rail. A high energy deep oxygen implant is performed to create a deep buried oxide layer and a first intermediate silicon layer. The deep buried oxide layer is disposed between the bulk silicon substrate layer and the first intermediate silicon layer. The first intermediate silicon layer defines another power distribution rail. A lower energy oxygen implant is performed to create a shallow buried oxide layer and a second intermediate silicon layer. The shallow buried oxide layer is disposed between the first intermediate silicon layer and the second intermediate silicon layer. A connection to the bulk silicon substrate layer is formed without making electrical connection to the intermediate silicon layers. A connection to the first intermediate silicon layer is formed without making electrical connection to the second intermediate silicon layer.

    摘要翻译： 提供了用于实现用于绝缘体上硅（SOI）器件的掩埋双轨配电和集成去耦电容的方法和半导体结构。 提供了限定一个配电轨的体硅衬底层。 执行高能深氧注入以产生深埋氧化层和第一中间硅层。 深埋氧化层设置在体硅衬底层和第一中间硅层之间。 第一中间硅层限定另一配电轨。 执行较低能量的氧注入以产生浅埋氧化物层和第二中间硅层。 浅埋氧化层设置在第一中间硅层和第二中间硅层之间。 形成与本体硅衬底层的连接，而不与中间硅层电连接。 形成与第一中间硅层的连接，而不与第二中间硅层电连接。

    Silicon-on-insulator (SOI) semiconductor structure for implementing transistor source connections using buried dual rail distribution
    10.
    发明授权
    Silicon-on-insulator (SOI) semiconductor structure for implementing transistor source connections using buried dual rail distribution 失效
    绝缘体上硅（SOI）半导体结构，用于使用埋地双轨配电实现晶体管源连接

    公开(公告)号：US06670716B2

    公开(公告)日：2003-12-30

    申请号：US10225914

    申请日：2002-08-22

    申请人： Todd Alan Christensen ,  John Edward Sheets, II ,  Gregory John Uhlmann

    发明人： Todd Alan Christensen ,  John Edward Sheets, II ,  Gregory John Uhlmann

    IPC分类号： H01V2348

    CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/84

    摘要： Silicon-on-insulator (SOI) semiconductor structures are provided for implementing transistor source connections for SOI transistor devices using buried dual rail distribution. A SOI semiconductor structure includes a SOI transistor having a silicide layer covering a SOI transistor source, a predefined buried conduction layer to be connected to a SOI transistor source, and an intermediate conduction layer between the SOI transistor and the predefined buried conduction layer. A first hole for a transistor source connection to a local interconnect is anisotropically etched in the SOI semiconductor structure to the silicide layer covering the SOI transistor source. A second hole aligned with the local interconnect hole is anisotropically etched through the SOI semiconductor structure to the predefined buried conduction layer. An insulator is disposed between the second hole and the intermediate conduction layer. A conductor is deposited in the first and second holes to create a transistor source connection to the predefined buried conduction layer in the SOI semiconductor structure.

    摘要翻译： 提供绝缘体上硅（SOI）半导体结构，用于实现使用埋置双轨分布的SOI晶体管器件的晶体管源连接。 SOI半导体结构包括具有覆盖SOI晶体管源的硅化物层的SOI晶体管，要连接到SOI晶体管源的预定掩埋导电层以及SOI晶体管和预定义的掩埋导电层之间的中间导电层。 用于与局部互连的晶体管源极连接的第一孔在SOI半导体结构中被各向异性蚀刻到覆盖SOI晶体管源的硅化物层。 与局部互连孔对准的第二孔通过SOI半导体结构被各向异性蚀刻到预定义的掩埋导电层。 绝缘体设置在第二孔和中间导电层之间。 导体沉积在第一和第二孔中以产生与SOI半导体结构中的预定掩埋导电层的晶体管源连接。