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    FinFET body contact structure
    4.
    发明授权
    FinFET body contact structure 有权
    FinFET体接触结构

    公开(公告)号：US07696565B2

    公开(公告)日：2010-04-13

    申请号：US11696331

    申请日：2007-04-04

    申请人： Richard Lee Donze ,  Karl Robert Erickson ,  William Paul Hovis ,  Terrance Wayne Kueper ,  John Edward Sheets, II ,  Jon Robert Tetzloff

    发明人： Richard Lee Donze ,  Karl Robert Erickson ,  William Paul Hovis ,  Terrance Wayne Kueper ,  John Edward Sheets, II ,  Jon Robert Tetzloff

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66795

    摘要： A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin portion. The polysilicon polygon shape has a center area having no polysilicon. FinFETs are formed on two vertical surfaces of the wide fin portion and gates of the FinFETs are coupled to the polysilicon polygon shape. Top surfaces of the wide fin portion and the polysilicon polygon shape are silicided. Silicide bridging is prevented by sidewall spacers. All convex angles on the polysilicon polygon shape are obtuse enough to prevent creation of bridging vertices. The center area is doped of an opposite type from a source and a drain of an associated FinFET.

    摘要翻译： 公开了FinFET体接触结构和用于产生FinFET体接触结构的方法。 本体接触结构包括半导体鳍片的宽鳍片部分，宽鳍片部分形成在宽鳍片部分的顶表面上的多晶硅多边形形状。 多晶硅多晶形状具有不具有多晶硅的中心区域。 FinFET形成在宽鳍片部分的两个垂直表面上，并且FinFET的栅极耦合到多晶硅多边形形状。 宽鳍片部分和多晶硅多边形形状的顶表面被硅化。 通过侧壁间隔物防止硅化物桥接。 多晶硅多边形形状上的所有凸角都足够钝，以防止桥接顶点的产生。 中心区域与相关联的FinFET的源极和漏极相反地掺杂。

    FinFET body contact structure
    5.
    发明授权
    FinFET body contact structure 有权
    FinFET体接触结构

    公开(公告)号：US07241649B2

    公开(公告)日：2007-07-10

    申请号：US10977768

    申请日：2004-10-29

    申请人： Richard Lee Donze ,  Karl Robert Erickson ,  William Paul Hovis ,  Terrance Wayne Kueper ,  John Edward Sheets, II ,  Jon Robert Tetzloff

    发明人： Richard Lee Donze ,  Karl Robert Erickson ,  William Paul Hovis ,  Terrance Wayne Kueper ,  John Edward Sheets, II ,  Jon Robert Tetzloff

    IPC分类号： H01L21/84

    CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66795

    摘要： A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin portion. The polysilicon polygon shape has a center area having no polysilicon. FinFETs are formed on two vertical surfaces of the wide fin portion and gates of the FinFETs are coupled to the polysilicon polygon shape. Top surfaces of the wide fin portion and the polysilicon polygon shape are silicided. Silicide bridging is prevented by sidewall spacers. All convex angles on the polysilicon polygon shape are obtuse enough to prevent creation of bridging vertices. The center area is doped of an opposite type from a source and a drain of an associated FinFET.

    摘要翻译： 公开了FinFET体接触结构和用于产生FinFET体接触结构的方法。 本体接触结构包括半导体鳍片的宽鳍片部分，宽鳍片部分形成在宽鳍片部分的顶表面上的多晶硅多边形形状。 多晶硅多晶形状具有不具有多晶硅的中心区域。 FinFET形成在宽鳍片部分的两个垂直表面上，并且FinFET的栅极耦合到多晶硅多边形形状。 宽鳍片部分和多晶硅多边形形状的顶表面被硅化。 通过侧壁间隔物防止硅化物桥接。 多晶硅多边形形状上的所有凸角都足够钝，以防止桥接顶点的产生。 中心区域与相关联的FinFET的源极和漏极相反地掺杂。

    Method and apparatus for improving performance margin in logic paths
    6.
    发明授权
    Method and apparatus for improving performance margin in logic paths 失效
    提高逻辑路径性能余量的方法和装置

    公开(公告)号：US07317605B2

    公开(公告)日：2008-01-08

    申请号：US10798911

    申请日：2004-03-11

    申请人： Richard Lee Donze ,  William Paul Hovis ,  Terrance Wayne Kueper ,  John Edward Sheets, II ,  Jon Robert Tetzloff

    发明人： Richard Lee Donze ,  William Paul Hovis ,  Terrance Wayne Kueper ,  John Edward Sheets, II ,  Jon Robert Tetzloff

    IPC分类号： H02H5/04

    CPC分类号： G11C5/147 ,  G06F1/206 ,  G06F1/26 ,  G11C7/04 ,  G11C11/4074

    摘要： An apparatus and method is disclosed for improving timing margins of logic paths on a semiconductor chip. Typical logic embodiments, such as CMOS (Complementary Metal Oxide Semiconductor), have path delays that become shorter as supply voltage is increased. Embodiments of the present invention store product data on each particular chip. The product data includes, for examples, but not limited to, a voltage range having a low limit voltage and a high limit voltage, a limit temperature, and performance of the particular chip in storage for the particular chip. Each chip has a voltage controller, a timer, and a thermal monitor. The voltage controller communicates with a voltage regulator and dynamically causes a voltage supply coupled to the chip to be as high as possible in the voltage range, subject to the limit temperature.

    摘要翻译： 公开了一种用于改善半导体芯片上的逻辑路径的时序余量的装置和方法。 诸如CMOS（互补金属氧化物半导体）的典型逻辑实施例具有随着电源电压增加而变短的路径延迟。 本发明的实施例将产品数​​据存储在每个特定芯片上。 产品数据包括例如但不限于具有用于特定芯片的存储器中的特定芯片的低限电压和上限电压，极限温度和性能的电压范围。 每个芯片都有一个电压控制器，一个定时器和一个热量监视器。 电压控制器与电压调节器通信，动态地使耦合到芯片的电压在电压范围内尽可能高，受限于极限温度。

    Polysilicon conductor width measurement for 3-dimensional FETs
    7.
    发明授权
    Polysilicon conductor width measurement for 3-dimensional FETs 失效
    三维FET的多晶硅导体宽度测量

    公开(公告)号：US07227183B2

    公开(公告)日：2007-06-05

    申请号：US10944622

    申请日：2004-09-17

    申请人： Richard Lee Donze ,  William Paul Hovis ,  Terrance Wayne Kueper ,  John Edward Sheets, II ,  Jon Robert Tetzloff

    发明人： Richard Lee Donze ,  William Paul Hovis ,  Terrance Wayne Kueper ,  John Edward Sheets, II ,  Jon Robert Tetzloff

    IPC分类号： H01L21/66

    CPC分类号： H01L27/1203 ,  H01L22/34 ,  H01L29/785

    摘要： An apparatus and method is disclosed for determining polysilicon conductor width for 3-dimensional field effect transistors (FinFETs). Two or more resistors are constructed using a topology in which polysilicon conductors are formed over a plurality of silicon “fins”. A first resistor has a first line width. A second resistor has a second line width. The second line width is slightly different than the first line width. Advantageously, the first line width is equal to the nominal design width used to make FET gates in the particular semiconductor technology. Resistance measurements of the resistors and subsequent calculations using the resistance measurements are used to determine the actual polysilicon conductor width produced by the semiconductor process. A composite test structure not only allows calculation of the polysilicon conductor width, but provides proof that differences in the widths used in the calculations do not introduce objectionable etching characteristics of the polysilicon conductors.

    摘要翻译： 公开了一种用于确定三维场效应晶体管（FinFET）的多晶硅导体宽度的装置和方法。 使用其中在多个硅“鳍”上形成多晶硅导体的拓扑构造两个或更多个电阻器。 第一电阻器具有第一线宽度。 第二电阻具有第二线宽。 第二行宽度与第一行宽度略有不同。 有利地，第一线宽度等于在特定半导体技术中用于制造FET栅极的标称设计宽度。 电阻的电阻测量和使用电阻测量的随后的计算用于确定由半导体工艺产生的实际多晶硅导体宽度。 复合测试结构不仅允许计算多晶硅导体宽度，而且提供了在计算中使用的宽度差不会引起多晶硅导体的不良刻蚀特性的证据。

    Method and apparatus to reduce bias temperature instability (BTI) effects
    8.
    发明授权
    Method and apparatus to reduce bias temperature instability (BTI) effects 失效
    降低偏倚温度不稳定性（BTI）效应的方法和装置

    公开(公告)号：US07009905B2

    公开(公告)日：2006-03-07

    申请号：US10744175

    申请日：2003-12-23

    申请人： Anthony Gus Aipperspach ,  William Paul Hovis ,  Terrance Wayne Kueper ,  John Edward Sheets, II

    发明人： Anthony Gus Aipperspach ,  William Paul Hovis ,  Terrance Wayne Kueper ,  John Edward Sheets, II

    IPC分类号： G11C7/04

    CPC分类号： G11C7/04 ,  G11C7/1045

    摘要： Methods and apparatus are disclosed that allow an electronic system implemented with field effect transistors (FETs) to reduce threshold voltage shifts caused by bias temperature instability (BTI). BTI caused VT shifts accumulate when an FET is in a particular voltage stress condition. Many storage elements in an electronic system store the same data for virtually the life of the system, resulting in significant BTI caused VT shifts in FETs in the storage elements. An embodiment of the invention ensures that a particular storage element is in a first state for a first portion of time the electronic system operates, during which data is stored in a storage element in a first phase, and that the particular storage element is in a second state for a second portion of time the electronic system operates, during which data is stored in the storage element in a second phase.

    摘要翻译： 公开了允许用场效应晶体管（FET）实现的电子系统减少由偏置温度不稳定性（BTI）引起的阈值电压偏移的方法和装置。 当FET处于特定的电压应力状态时，BTI引起VT偏移累加。 电子系统中的许多存储元件几乎在系统中存储相同的数据，导致显着的BTI导致存储元件中FET的VT位移。 本发明的一个实施例确保了特定存储元件在电子系统操作的第一时间段处于第一状态，在此期间数据被存储在第一阶段的存储元件中，并且特定存储元件处于 电子系统操作的第二部分时间的第二状态，在此期间数据以第二阶段存储在存储元件中。

    Measurement of bias of a silicon area using bridging vertices on polysilicon shapes to create an electrical open/short contact structure
    9.
    发明授权
    Measurement of bias of a silicon area using bridging vertices on polysilicon shapes to create an electrical open/short contact structure 失效
    使用多晶硅形状上的桥接顶点测量硅区域的偏置，以产生电开/短接触结构

    公开(公告)号：US07336086B2

    公开(公告)日：2008-02-26

    申请号：US11559949

    申请日：2006-11-15

    申请人： Richard Lee Donze ,  Karl Robert Erickson ,  William Paul Hovis ,  John Edward Sheets, II ,  Jon Robert Tetzloff

    发明人： Richard Lee Donze ,  Karl Robert Erickson ,  William Paul Hovis ,  John Edward Sheets, II ,  Jon Robert Tetzloff

    IPC分类号： G01R31/26 ,  H01L23/58 ,  H01L21/66

    CPC分类号： H01L22/34 ,  H01L29/785

    摘要： An apparatus and method are disclosed for measuring bias of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon area create low resistance connections between those bridging vertices and the silicon area; other bridging vertices over ROX (recessed oxide) areas do not create low resistance connections between those other bridging vertices and the silicon area. Determining which bridging vertices have low resistance connections to the silicon area and how many bridging vertices have low resistance connections to the silicon area are used to determine the bias of the polysilicon shapes relative to the silicon area.

    摘要翻译： 公开了一种用于测量多晶硅形状相对于硅区域的偏置的装置和方法，其中使用电耦合的存在来确定偏置的存在。 形成多晶硅形状上的桥接顶点。 在硅区域上的桥接顶点在这些桥接顶点和硅区域之间产生低电阻连接; ROX（凹陷氧化物）区域上的其他桥接顶点不会在其他桥接顶点和硅区域之间产生低电阻连接。 确定哪些桥接顶点具有与硅区域的低电阻连接以及有多少桥接顶点具有与硅区域的低电阻连接，以确定多晶硅形状相对于硅面积的偏置。

    Electrical open/short contact alignment structure for active region vs. gate region
    10.
    发明授权
    Electrical open/short contact alignment structure for active region vs. gate region 失效
    用于有源区域与栅极区域的电开/短接触对准结构

    公开(公告)号：US07183780B2

    公开(公告)日：2007-02-27

    申请号：US10944625

    申请日：2004-09-17

    申请人： Richard Lee Donze ,  Karl Robert Erickson ,  William Paul Hovis ,  John Edward Sheets, II ,  Jon Robert Tetzloff

    发明人： Richard Lee Donze ,  Karl Robert Erickson ,  William Paul Hovis ,  John Edward Sheets, II ,  Jon Robert Tetzloff

    IPC分类号： G01R27/08 ,  G01R31/26 ,  H01L23/58 ,  H01L21/66

    CPC分类号： H01L22/34 ,  H01L29/785

    摘要： An apparatus for measuring alignment of polysilicon shapes to a silicon area. Each polysilicon shape in a first plurality of polysilicon shapes has a bridging vertex positioned near the silicon area. Each polysilicon shape in a second plurality of polysilicon shapes has a bridging vertex positioned near the silicon area. The second plurality of silicon shapes is positioned on the opposite side of the silicon area from the first plurality of silicon shapes. An electrical measurement of how many of the polysilicon shapes in the first plurality of polysilicon shapes and in the second plurality of polysilicon shapes provides a measurement of alignment of the polysilicon shapes and the silicon area.

    摘要翻译： 一种用于测量多晶硅形状与硅区域的取向的装置。 第一多个多晶硅形状中的每个多晶硅形状具有位于硅区附近的桥接顶点。 第二多晶硅形状中的每个多晶硅形状具有位于硅区附近的桥接顶点。 第二多个硅形状位于硅区域与第一多个硅形状的相对侧上。 第一多晶硅形状中的多晶硅形状和第二多晶硅形状中的多晶硅形状的电测量提供了多晶硅形状和硅区域的对准的测量。