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公开(公告)号：US07072229B2
公开(公告)日：2006-07-04
申请号：US11150585
申请日：2005-06-13
申请人： Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge , Dennis Michael Sylvester , Krisztian Flautner
发明人： Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge , Dennis Michael Sylvester , Krisztian Flautner
IPC分类号： G11C7/00
CPC分类号： G06F9/3869 , G06F9/3861 , G06F11/141 , G11C7/04 , G11C7/1006 , G11C7/1039 , G11C7/1045 , G11C7/22 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C2207/2281
摘要： There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism; a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.
摘要翻译： 提供了一种用于存储数据的存储器，包括：快速数据读取机构，用于从所述存储器读取数据值，以产生从所述存储器输出的快速读取结果用于进一步处理; 缓慢的数据读取机构，用于从所述存储器读取所述数据值，以产生在所述快速读取结果被输出以供进一步处理之后可用的慢速读取结果，所述慢速数据读取机构在读取所述数据值时不太容易出现所述数据值 快速数据读取机制; 比较器，用于比较所述快速读取结果和所述慢速读取结果，以检测所述快速读取结果是否与所述慢速读取结果不同; 如果所述比较器检测到所述快速读取结果不同于所述慢速读取结果以便使用所述快速读取结果抑制所述进一步处理，则输出所述慢速读取结果代替所述快速读取结果并重启所述进一步处理的错误修复逻辑 基于所述慢读取结果。
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公开(公告)号：US06944067B2
公开(公告)日：2005-09-13
申请号：US10779809
申请日：2004-02-18
申请人： Trevor Nigel Mudge , Todd Michael Austin , David Theodore Blaauw , Dennis Michael Sylvester , Krisztian Flautner
发明人： Trevor Nigel Mudge , Todd Michael Austin , David Theodore Blaauw , Dennis Michael Sylvester , Krisztian Flautner
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , G11C2207/2281 , Y02D10/126 , Y02D10/128 , Y02D10/171
摘要： There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said, fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.
摘要翻译： 提供了一种用于存储数据的存储器，包括：快速数据读取机构，用于从所述存储器读取数据值，以产生从所述存储器输出的快速读取结果用于进一步处理; 缓慢的数据读取机构，用于从所述存储器读取所述数据值，以产生在所述快速读取结果被输出以供进一步处理之后可用的慢速读取结果，所述慢速数据读取机构在读取所述数据值时不太容易出现所述数据值 快速数据读取机构，比较器，用于比较所述快速读取结果和所述慢速读取结果，以检测所述快速读取结果是否与所述慢速读取结果不同; 如果所述比较器检测到所述快速读取结果与所述慢速读取结果不同，以便使用所述快速读取结果抑制所述进一步处理，则输出所述慢速读取结果代替所述快速读取结果并重新启动所述更多读取结果的错误修复逻辑 基于所述慢读取结果进行处理。
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公开(公告)号：US08230152B2
公开(公告)日：2012-07-24
申请号：US12458511
申请日：2009-07-14
IPC分类号： G06F13/00
CPC分类号： G11C7/10
摘要： Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection.
摘要翻译： 交叉开关电路以及这种交叉电路的操作方法。 交叉开关电路具有数据输入路径和数据输出路径的阵列，其中数据输出路径横向于数据输入路径。 在数据输入路径和数据输出路径之间的每个交点处，提供交叉开关单元，其包括可编程以存储路由值的配置存储电路，传输电路和仲裁电路。 在传输操作模式中，传输电路响应于路由值是第一值，指示数据输入路径应耦合到数据输出路径，以检测沿数据输入路径输入的数据，并输出 在相关联的交叉路口上的数据输出路径上的该数据的指示。
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4.发明申请Crossbar circuitry for applying an adaptive priority scheme and method of operation of such crossbar circuitry 有权用于应用自适应优先权方案的交叉开关电路和这种交叉电路的操作方法公开(公告)号：US20110138098A1
公开(公告)日：2011-06-09
申请号：US12926462
申请日：2010-11-18
IPC分类号： G06F13/00
CPC分类号： G11C7/10 , H03K17/693
摘要： Crossbar circuitry has an array of data input and output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided which includes a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. In an arbitration mode of operation, the arbitration circuitry is operable to selectively modify the voltage on said plurality of bit lines in order to apply an adaptive priority scheme.
摘要翻译： 交叉开关电路具有数据输入和输出路径阵列，其中数据输出路径横向于数据输入路径。 在数据输入路径和数据输出路径之间的每个交点处，提供交叉开关单元，其包括可编程以存储路由值的配置存储电路，发送电路和仲裁电路。 在传输操作模式中，传输电路响应于路由值是第一值，指示数据输入路径应耦合到数据输出路径，以检测沿数据输入路径输入的数据，并输出 在相关联的交叉路口上的数据输出路径上的该数据的指示。 在仲裁操作模式中，仲裁电路可操作以选择性地修改所述多个位线上的电压，以便应用自适应优先级方案。
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5.发明授权Crossbar circuitry for applying an adaptive priority scheme and method of operation of such crossbar circuitry 有权用于应用自适应优先权方案的交叉开关电路和这种交叉电路的操作方法公开(公告)号：US08549207B2
公开(公告)日：2013-10-01
申请号：US12926462
申请日：2010-11-18
CPC分类号： G11C7/10 , H03K17/693
摘要： Crossbar circuitry has an array of data input and output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided which includes a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. In an arbitration mode of operation, the arbitration circuitry is operable to selectively modify the voltage on said plurality of bit lines in order to apply an adaptive priority scheme.
摘要翻译： 交叉开关电路具有数据输入和输出路径阵列，其中数据输出路径横向于数据输入路径。 在数据输入路径和数据输出路径之间的每个交点处，提供交叉开关单元，其包括可编程以存储路由值的配置存储电路，发送电路和仲裁电路。 在传输操作模式中，传输电路响应于路由值是第一值，指示数据输入路径应耦合到数据输出路径，以检测沿数据输入路径输入的数据，并输出 在相关联的交叉路口上的数据输出路径上的该数据的指示。 在仲裁操作模式中，仲裁电路可操作以选择性地修改所述多个位线上的电压，以便应用自适应优先级方案。
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6.发明申请Crossbar circuitry for applying a pre-selection prior to arbitration between transmission requests and method of operation of such crossbar circuitry 有权交叉开关电路，用于在传输请求和这种交叉电路的操作方法之前的仲裁之前应用预选择公开(公告)号：US20120047310A1
公开(公告)日：2012-02-23
申请号：US13137487
申请日：2011-08-19
IPC分类号： G06F13/00
CPC分类号： G11C7/10 , G11C7/1006 , H03K17/693
摘要： Crossbar circuitry has data input and output paths, and at each intersection between a data input and output path, a crossbar cell is provided. A transmission circuit is responsive to a stored routing value to couple a data input path to a selected data output path. Pre-selection circuitry cooperates with the pre-selection circuits of other crossbar cells on the same data output path to use the bit lines of the data output path to compare quality-of-service values associated with multiple asserted transmission requests and to determine a subset thereof which have a highest value of the quality-of-service values. Arbitration circuitry implements a predetermined priority scheme to choose from that subset of requests and to cause the configuration storage circuit of only one crossbar cell associated with the same data output path to have its routing value programmed to the first value, thereby resolving conflict between multiple asserted transmission requests.
摘要翻译： 交叉开关电路具有数据输入和输出路径，并且在数据输入和输出路径之间的每个交叉点处，提供交叉开关单元。 传输电路响应于存储的路由值以将数据输入路径耦合到所选择的数据输出路径。 预选电路与同一数据输出路径上的其他交叉开关单元的预选电路配合使用数据输出路径的位线来比较与多个被断言的传输请求相关联的服务质量值，并确定子集 它们具有最高的服务质量值。 仲裁电路实现预定的优先权方案以从该请求子集中选择，并且使与仅相邻数据输出路径相关联的一个交叉开关单元的配置存储电路将其路由值编程为第一值，从而解决多个被断言的 传输请求
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公开(公告)号：US20100211720A1
公开(公告)日：2010-08-19
申请号：US12458511
申请日：2009-07-14
CPC分类号： G11C7/10
摘要： Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. In an arbitration mode of operation, the arbitration circuitry is operable in the presence of an asserted transmission request from the associated source circuit to operate in combination with the arbitration circuits of other crossbar cells associated with the same data output path to re-use the bit lines of the data output path to detect the presence of multiple asserted transmission requests for the same data output path. In the event of such multiple asserted transmission requests, the arbitration circuitry operates in combination with the other arbitration circuits to implement a predetermined priority scheme to cause the configuration storage circuit of only one crossbar cell associated with the same data output path to have its routing value programmed to the first value, thereby resolving conflict between the multiple asserted transmission requests according to the predetermined priority scheme. Such a construction of crossbar circuitry enables a very efficient resolution of conflicts to be performed, whilst providing a very regular design, with uniform delay across all paths, and which requires significantly less control lines that typical prior art crossbar designs. Such crossbar circuitry is readily scalable to form large crossbars.
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公开(公告)号：US08108585B2
公开(公告)日：2012-01-31
申请号：US12379191
申请日：2009-02-13
申请人： Sudhir Kumar Satpathy , David Theodore Blaauw , Trevor Nigel Mudge , Dennis Michael Sylvester , Ronald George Dreslinski, Jr.
发明人： Sudhir Kumar Satpathy , David Theodore Blaauw , Trevor Nigel Mudge , Dennis Michael Sylvester , Ronald George Dreslinski, Jr.
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a storage circuit programmable to store a routing value, and a transmission circuit. In a transmission mode of operation the transmission circuit is responsive to the routing value indicating that the data input path should be coupled to the data output path to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. Control circuitry is used to issue control signals to the crossbar cells, and during a configuration mode of operation the control circuitry re-utilizes at least one of the data output paths to program the storage circuitry of one or more of the crossbar cells. Such a construction of crossbar circuitry provides a very regular design, with uniform delay across all paths, and which requires significantly less control lines than typical prior art crossbar designs. Such crossbar circuitry is readily scalable to form large crossbars.
摘要翻译： 交叉开关电路以及这种交叉电路的操作方法。 交叉开关电路具有数据输入路径和数据输出路径的阵列，其中数据输出路径横向于数据输入路径。 在数据输入路径和数据输出路径之间的每个交叉点处，提供包括可编程以存储路由值的存储电路的交叉开关单元和发送电路。 在传输操作模式中，传输电路响应于路由值，该路由值指示数据输入路径应该被耦合到数据输出路径以检测沿着数据输入路径的数据输入，并且输出该数据的指示 相关联的交叉路口的数据输出路径。 控制电路用于向交叉开关单元发出控制信号，并且在配置操作模式期间，控制电路重新利用至少一个数据输出路径来编程一个或多个交叉开关单元的存储电路。 交叉电路电路的这种结构提供非常规则的设计，在所有路径上具有均匀的延迟，并且其需要比典型的现有技术的横杆设计明显更少的控制线。 这种交叉开关电路容易缩放以形成大的横杆。
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9.发明授权Crossbar circuitry for applying an adaptive priority scheme and method of operation of such crossbar circuitry 有权用于应用自适应优先权方案的交叉开关电路和这种交叉电路的操作方法公开(公告)号：US08868817B2
公开(公告)日：2014-10-21
申请号：US13438920
申请日：2012-04-04
IPC分类号： G06F13/00 , G11C7/10 , G06F13/40 , H03K17/693
CPC分类号： G11C7/10 , G06F13/4022 , G06F2213/0038 , G11C7/1012 , H03K17/693
摘要： Interconnect circuitry 2 has a plurality of data source circuits 8 connected to respective input paths 4 and a plurality of data destination circuits 10 connected to respective output paths 6. Connection cells 12 provide selective connections between input paths 4 and output paths 6. Arbitration circuitry 26 provides adaptive priority arbitration between overlapping requests received at different input paths. Priority bits 16 within a matrix of priority bit 46 for each output path 10 are used to represent the priority relationships between different input paths which compete for access to that output path 10. Update operations are applied on a per row or per column basis within the matrix to implement update schemes such as least recently granted, most recently granted, round robin, reversal, swap, selective least recently granted, selective most recently granted etc.
摘要翻译： 互连电路2具有连接到相应输入路径4的多个数据源电路8和连接到相应输出路径6的多个数据目的地电路10.连接单元12提供输入路径4和输出路径6之间的选择性连接。仲裁电路26 在不同输入路径上接收的重叠请求之间提供自适应优先级仲裁。 用于每个输出路径10的优先级位46的矩阵内的优先级位16用于表示竞争对该输出路径10的访问的不同输入路径之间的优先级关系。更新操作按照每行或每列进行应用 矩阵来实现更新计划，例如最近最近授予的，最近授予的，轮回，逆转，掉期，最少选择权，最近授予的选择权。
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公开(公告)号：US08255610B2
公开(公告)日：2012-08-28
申请号：US13137487
申请日：2011-08-19
IPC分类号： G06F13/00
CPC分类号： G11C7/10 , G11C7/1006 , H03K17/693
摘要： Crossbar circuitry has data input and output paths, and at each intersection between a data input and output path, a crossbar cell is provided. A transmission circuit is responsive to a stored routing value to couple a data input path to a selected data output path. Pre-selection circuitry cooperates with the pre-selection circuits of other crossbar cells on the same data output path to use the bit lines of the data output path to compare quality-of-service values associated with multiple asserted transmission requests and to determine a subset thereof which have a highest value of the quality-of-service values. Arbitration circuitry implements a predetermined priority scheme to choose from that subset of requests and to cause the configuration storage circuit of only one crossbar cell associated with the same data output path to have its routing value programmed to the first value, thereby resolving conflict between multiple asserted transmission requests.
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