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    Memory system having fast and slow data reading mechanisms
    1.
    发明授权
    Memory system having fast and slow data reading mechanisms 有权
    内存系统具有快速和慢速的数据读取机制

    公开(公告)号：US07072229B2

    公开(公告)日：2006-07-04

    申请号：US11150585

    申请日：2005-06-13

    申请人： Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  Dennis Michael Sylvester ,  Krisztian Flautner

    发明人： Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  Dennis Michael Sylvester ,  Krisztian Flautner

    IPC分类号： G11C7/00

    CPC分类号： G06F9/3869 ,  G06F9/3861 ,  G06F11/141 ,  G11C7/04 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/22 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2207/2281

    摘要： There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism; a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.

    摘要翻译： 提供了一种用于存储数据的存储器，包括：快速数据读取机构，用于从所述存储器读取数据值，以产生从所述存储器输出的快速读取结果用于进一步处理; 缓慢的数据读取机构，用于从所述存储器读取所述数据值，以产生在所述快速读取结果被输出以供进一步处理之后可用的慢速读取结果，所述慢速数据读取机构在读取所述数据值时不太容易出现所述数据值 快速数据读取机制; 比较器，用于比较所述快速读取结果和所述慢速读取结果，以检测所述快速读取结果是否与所述慢速读取结果不同; 如果所述比较器检测到所述快速读取结果不同于所述慢速读取结果以便使用所述快速读取结果抑制所述进一步处理，则输出所述慢速读取结果代替所述快速读取结果并重启所述进一步处理的错误修复逻辑 基于所述慢读取结果。

    Memory system having fast and slow data reading mechanisms
    2.
    发明授权
    Memory system having fast and slow data reading mechanisms 有权
    内存系统具有快速和慢速的数据读取机制

    公开(公告)号：US06944067B2

    公开(公告)日：2005-09-13

    申请号：US10779809

    申请日：2004-02-18

    申请人： Trevor Nigel Mudge ,  Todd Michael Austin ,  David Theodore Blaauw ,  Dennis Michael Sylvester ,  Krisztian Flautner

    发明人： Trevor Nigel Mudge ,  Todd Michael Austin ,  David Theodore Blaauw ,  Dennis Michael Sylvester ,  Krisztian Flautner

    IPC分类号： G06F1/32 ,  G11C7/00

    CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/3287 ,  G11C2207/2281 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/171

    摘要： There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said, fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.

    摘要翻译： 提供了一种用于存储数据的存储器，包括：快速数据读取机构，用于从所述存储器读取数据值，以产生从所述存储器输出的快速读取结果用于进一步处理; 缓慢的数据读取机构，用于从所述存储器读取所述数据值，以产生在所述快速读取结果被输出以供进一步处理之后可用的慢速读取结果，所述慢速数据读取机构在读取所述数据值时不太容易出现所述数据值 快速数据读取机构，比较器，用于比较所述快速读取结果和所述慢速读取结果，以检测所述快速读取结果是否与所述慢速读取结果不同; 如果所述比较器检测到所述快速读取结果与所述慢速读取结果不同，以便使用所述快速读取结果抑制所述进一步处理，则输出所述慢速读取结果代替所述快速读取结果并重新启动所述更多读取结果的错误修复逻辑 基于所述慢读取结果进行处理。

    Integrated circuit with error correction mechanisms to offset narrow tolerancing
    3.
    发明授权
    Integrated circuit with error correction mechanisms to offset narrow tolerancing 有权
    具有纠错机制的集成电路，以抵消窄公差

    公开(公告)号：US07701240B2

    公开(公告)日：2010-04-20

    申请号：US11301240

    申请日：2005-12-13

    申请人： Krisztian Flautner ,  David Michael Bull ,  Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge

    发明人： Krisztian Flautner ,  David Michael Bull ,  Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge

    IPC分类号： G01R31/26 ,  G01R31/28

    CPC分类号： G06F11/24

    摘要： An integrated circuit 2 has a specified range of runtime-variable operating parameters. Data processing circuits 4 within the integrated circuit 2 have associated error detection and error repair mechanisms 6. When operating within a narrow typical-case range of runtime-variable operating parameters the data processing circuits 4 operate correctly and substantially without error. When operating outside of this typical-case range but inside the specified range of permitted values for the run-time variable operating parameters, then the error detection and error repair circuit 6 operate to repair the errors which occur.

    摘要翻译： 集成电路2具有指定范围的运行时变量运行参数。 集成电路2内的数据处理电路4具有相关联的错误检测和错误修复机制6.当在运行时间可变的运行参数的窄典型情况范围内操作时，数据处理电路4正确且基本上没有错误地操作。 当在这种典型情况范围之外运行，但在运行时变量运行参数的允许值的指定范围内时，错误检测和错误修复电路6操作以修复发生的错误。

    Data retention latch provision within integrated circuits
    4.
    发明授权
    Data retention latch provision within integrated circuits 有权
    集成电路内的数据保持锁存器提供

    公开(公告)号：US07310755B2

    公开(公告)日：2007-12-18

    申请号：US10779817

    申请日：2004-02-18

    申请人： Trevor Nigel Mudge ,  Todd Michael Austin ,  David Theodore Blaauw ,  Krisztian Flautner

    发明人： Trevor Nigel Mudge ,  Todd Michael Austin ,  David Theodore Blaauw ,  Krisztian Flautner

    IPC分类号： G01R31/28 ,  H03K3/00

    CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/3287 ,  G11C2207/2281 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/171

    摘要： An integrated circuit having a plurality of processing stages includes a low power mode controller operable to control the integrated circuit to switch between an operational mode and a standby mode. At least one of the processing stages has a non-delayed latch to capture a non-delayed value of an output signal from that processing stage and a delayed latch operable during the operational mode to capture a delayed value of the same signal. A difference between these two captured signals is indicative of the processing operation not being completed at the time the non-delayed signal was captured. The delayed latch is operable during the standby mode to retain the signal it captured whilst the non-delayed latch is powered down and loses its value. The delayed latch is formed to have a lower power consumption than the non-delayed latch.

    摘要翻译： 具有多个处理级的集成电路包括可操作以控制集成电路在操作模式和待机模式之间切换的低功率模式控制器。 处理级中的至少一个具有非延迟锁存器，以捕获来自该处理级的输出信号的非延迟值，以及在操作模式期间可操作以捕获相同信号的延迟值的延迟锁存器。 这两个捕获信号之间的差异表示在捕获非延迟信号时处理操作未完成。 延迟锁存器在待机模式期间可操作以保持其捕获的信号，同时非延迟锁存器断电并失去其值。 延迟锁存器形成为具有比非延迟锁存器更低的功耗。

    Error recovery within processing stages of an integrated circuit
    5.
    发明授权
    Error recovery within processing stages of an integrated circuit 有权
    集成电路处理阶段内的错误恢复

    公开(公告)号：US08185786B2

    公开(公告)日：2012-05-22

    申请号：US12923911

    申请日：2010-10-13

    申请人： Krisztian Flautner ,  Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge

    发明人： Krisztian Flautner ,  Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1695 ,  G06F11/0721 ,  G06F11/0793 ,  G06F11/104 ,  G06F11/1608 ,  G06F11/167 ,  G06F11/183

    摘要： An integrated circuit includes a plurality of processing stages each including processing logic, a non-delayed signal-capture element, a delayed signal-capture element and a comparator. The non-delayed signal-capture element captures an output from the processing logic at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element also captures a value from the processing logic. An error detection circuit and error correction circuit detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator. The comparator compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.

    摘要翻译： 集成电路包括多个处理级，每个处理级包括处理逻辑，非延迟信号捕获元件，延迟信号捕获元件和比较器。 非延迟信号捕获元件在非延迟捕获时间捕获来自处理逻辑的输出。 在稍后的延迟捕获时间，延迟信号捕获元件还捕获来自处理逻辑的值。 误差检测电路和误差校正电路检测并校正延迟值中的随机误差，并向比较器提供经错误检测的延迟值。 比较器比较错误检查的延迟值和非延迟值，如果它们不相等，则表示非延迟值被捕获太早，应由错误检查的延迟值替换。 非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播 在重新启动时钟之前通过后续的处理逻辑。 调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

    Systematic and random error detection and recovery within processing stages of an integrated circuit
    6.
    发明授权
    Systematic and random error detection and recovery within processing stages of an integrated circuit 有权
    在集成电路的处理阶段内的系统和随机的错误检测和恢复

    公开(公告)号：US07337356B2

    公开(公告)日：2008-02-26

    申请号：US10896997

    申请日：2004-07-23

    申请人： Trevor Nigel Mudge ,  Todd Michael Austin ,  David Theodore Blaauw ,  Krisztian Flautner

    发明人： Trevor Nigel Mudge ,  Todd Michael Austin ,  David Theodore Blaauw ,  Krisztian Flautner

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1695 ,  G06F9/3861 ,  G06F9/3869 ,  G06F11/0721 ,  G06F11/0793 ,  G06F11/104 ,  G06F11/1608 ,  G06F11/167 ,  G06F11/183

    摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.

    摘要翻译： 集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024。 非延迟信号捕获元件1016在非延迟捕获时间捕获来自处理逻辑1014的输出。 在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。 误差检测电路1026和误差校正电路1028检测并校正延迟值中的随机误差，并将错误检测的延迟值提供给比较器1024。 比较器1024比较错误检查的延迟值和非延迟值，如果它们不相等，则表示非延迟值被捕获得太早，应该被错误检查的延迟值替换。 非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播 在重新启动时钟之前通过后续的处理逻辑。 调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

    Error recovery within processing stages of an integrated circuit
    8.
    发明申请
    Error recovery within processing stages of an integrated circuit 有权

    公开(公告)号：US20110093737A1

    公开(公告)日：2011-04-21

    申请号：US12923911

    申请日：2010-10-13

    申请人： Krisztian Flautner ,  Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge

    发明人： Krisztian Flautner ,  Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge

    IPC分类号： G06F11/07

    CPC分类号： G06F11/1695 ,  G06F11/0721 ,  G06F11/0793 ,  G06F11/104 ,  G06F11/1608 ,  G06F11/167 ,  G06F11/183

    摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.

    Error detection and recovery within processing stages of an integrated circuit
    9.
    发明授权
    Error detection and recovery within processing stages of an integrated circuit 有权
    集成电路处理阶段内的错误检测和恢复

    公开(公告)号：US07650551B2

    公开(公告)日：2010-01-19

    申请号：US11889759

    申请日：2007-08-16

    申请人： Krisztian Flautner ,  Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge

    发明人： Krisztian Flautner ,  Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge

    IPC分类号： G01R31/28 ,  G11C29/00

    CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/3287 ,  G11C2207/2281 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/171

    摘要： An integrated circuit includes a plurality of processing stages each including processing logic 2, a non-delayed latch 4, a delayed latch 8 and a comparator 6. The non-delayed latch 4 captures an output from the processing logic 2 at a non-delayed capture time. At a later delayed capture time, the delayed latch 8 also captures a value from the processing logic 2. The comparator 6 compares these values and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.

    摘要翻译： 集成电路包括多个处理级，每个处理级包括处理逻辑2，非延迟锁存器4，延迟锁存器8和比较器6.非延迟锁存器4以非延迟捕获来自处理逻辑2的输出 捕捉时间。 在稍后的延迟捕获时间，延迟锁存器8也从处理逻辑2中捕获一个值。比较器6比较这些值，如果它们不相等，则表示非延迟值被捕获得太早，应该由 延迟值。 非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播 在重新启动时钟之前通过后续的处理逻辑。 调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。