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公开(公告)号：US08385124B2
公开(公告)日：2013-02-26
申请号：US13075169
申请日：2011-03-29
IPC分类号： G11C16/04
CPC分类号： H01L21/28282 , G11C16/0466 , H01L27/11573 , H01L29/42344 , H01L29/66833 , H01L29/78 , H01L29/792
摘要： The semiconductor device includes the nonvolatile memory cell in the main surface of a semiconductor substrate. The nonvolatile memory cell has a first insulating film over the semiconductor substrate, a conductive film, a second insulating film, the charge storage film capable of storing therein charges, a third insulating film over the charge storage film, a first gate electrode, a fourth insulating film in contact with the set of stacked films from the first insulating film to the foregoing first gate electrode, a fifth insulating film juxtaposed with the first insulating film over the foregoing semiconductor substrate, a second gate electrode formed over the fifth insulating film to be adjacent to the foregoing first gate electrode over the side surface of the fourth insulating film, and source/drain regions with the first and second gate electrodes interposed therebetween. The conductive film and the charge storage film are formed to two-dimensionally overlap.
摘要翻译： 半导体器件包括在半导体衬底的主表面中的非易失性存储单元。 非易失性存储单元在半导体衬底上具有第一绝缘膜，导电膜，第二绝缘膜，能够存储电荷的电荷存储膜，电荷存储膜上的第三绝缘膜，第一栅电极，第四绝缘膜 绝缘膜与从第一绝缘膜到前述第一栅电极的层叠膜接触;第五绝缘膜，与上述半导体衬底上的第一绝缘膜并置，形成在第五绝缘膜上的第二栅电极， 与第四绝缘膜的侧表面上的上述第一栅电极相邻，以及其间插入第一和第二栅电极的源/漏区。 导电膜和电荷存储膜形成为二维重叠。
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公开(公告)号：US20110242888A1
公开(公告)日：2011-10-06
申请号：US13075169
申请日：2011-03-29
IPC分类号： G11C11/34 , H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , G11C16/0466 , H01L27/11573 , H01L29/42344 , H01L29/66833 , H01L29/78 , H01L29/792
摘要： The semiconductor device includes the nonvolatile memory cell in the main surface of a semiconductor substrate. The nonvolatile memory cell has a first insulating film over the semiconductor substrate, a conductive film, a second insulating film, the charge storage film capable of storing therein charges, a third insulating film over the charge storage film, a first gate electrode, a fourth insulating film in contact with the set of stacked films from the first insulating film to the foregoing first gate electrode, a fifth insulating film juxtaposed with the first insulating film over the foregoing semiconductor substrate, a second gate electrode formed over the fifth insulating film to be adjacent to the foregoing first gate electrode over the side surface of the fourth insulating film, and source/drain regions with the first and second gate electrodes interposed therebetween. The conductive film and the charge storage film are formed to two-dimensionally overlap.
摘要翻译： 半导体器件包括在半导体衬底的主表面中的非易失性存储单元。 非易失性存储单元在半导体衬底上具有第一绝缘膜，导电膜，第二绝缘膜，能够存储电荷的电荷存储膜，电荷存储膜上的第三绝缘膜，第一栅电极，第四绝缘膜 绝缘膜与从第一绝缘膜到前述第一栅电极的层叠膜接触;第五绝缘膜，与上述半导体衬底上的第一绝缘膜并置，形成在第五绝缘膜上的第二栅电极， 与第四绝缘膜的侧表面上的上述第一栅电极相邻，以及其间插入第一和第二栅电极的源/漏区。 导电膜和电荷存储膜形成为二维重叠。
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3.发明授权公开(公告)号：US08409949B2
公开(公告)日：2013-04-02
申请号：US12822157
申请日：2010-06-23
IPC分类号： H01L21/336
CPC分类号： H01L29/42328 , G11C16/3418 , H01L27/11521 , H01L27/1203 , H01L29/7883
摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).
摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。
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4.发明申请公开(公告)号：US20090134449A1
公开(公告)日：2009-05-28
申请号：US12273308
申请日：2008-11-18
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/42328 , G11C16/3418 , H01L27/11521 , H01L27/1203 , H01L29/7883
摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).
摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。
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5.发明申请公开(公告)号：US20080142876A1
公开(公告)日：2008-06-19
申请号：US11943909
申请日：2007-11-21
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/115 , G11C16/0466 , H01L27/11521 , H01L27/11524 , H01L29/7851
摘要： A charge trapping layer in an element isolation region and that in an isolation region between a memory transistor and a selection transistor are removed so that the charges are not injected or trapped in the regions. Also, in an element isolation region, gate electrodes of each memory transistor are united at a position higher than a gate electrode of the selection transistor from a surface of a silicon substrate in an element isolation region, thereby reducing the capacitance between the memory transistor and the selection transistor.
摘要翻译： 去除元件隔离区域中的电荷捕获层，以及在存储晶体管和选择晶体管之间的隔离区域中的电荷捕获层，使得电荷不被注入或被捕获在该区域中。 此外，在元件隔离区域中，每个存储晶体管的栅极电极从元件隔离区域中的硅衬底的表面在选择晶体管的栅电极的高位置处结合，从而减小存储晶体管和 选择晶体管。
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6.发明申请公开(公告)号：US20100261327A1
公开(公告)日：2010-10-14
申请号：US12822157
申请日：2010-06-23
IPC分类号： H01L21/336
CPC分类号： H01L29/42328 , G11C16/3418 , H01L27/11521 , H01L27/1203 , H01L29/7883
摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).
摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。
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7.发明授权公开(公告)号：US07759720B2
公开(公告)日：2010-07-20
申请号：US12273308
申请日：2008-11-18
IPC分类号： H01L29/94
CPC分类号： H01L29/42328 , G11C16/3418 , H01L27/11521 , H01L27/1203 , H01L29/7883
摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).
摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。
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8.发明授权公开(公告)号：US07687845B2
公开(公告)日：2010-03-30
申请号：US11943909
申请日：2007-11-21
IPC分类号： H01L29/76 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0466 , H01L27/11521 , H01L27/11524 , H01L29/7851
摘要： A charge trapping layer in an element isolation region and that in an isolation region between a memory transistor and a selection transistor are removed so that the charges are not injected or trapped in the regions. Also, in an element isolation region, gate electrodes of each memory transistor are united at a position higher than a gate electrode of the selection transistor from a surface of a silicon substrate in an element isolation region, thereby reducing the capacitance between the memory transistor and the selection transistor.
摘要翻译： 去除元件隔离区域中的电荷捕获层，以及在存储晶体管和选择晶体管之间的隔离区域中的电荷捕获层，使得电荷不被注入或被捕获在该区域中。 此外，在元件隔离区域中，每个存储晶体管的栅极电极从元件隔离区域中的硅衬底的表面在选择晶体管的栅电极的高位置处结合，从而减小存储晶体管和 选择晶体管。
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公开(公告)号：US20090052259A1
公开(公告)日：2009-02-26
申请号：US12194433
申请日：2008-08-19
IPC分类号： G11C11/34
CPC分类号： G11C5/14 , G11C5/025 , G11C5/063 , G11C16/0425 , G11C16/0483 , G11C16/10
摘要： A non-volatile semiconductor memory device is provided. A gate electrode configuring a memory cell is turned into floating state and a potential of a gate electrode adjacent thereto is changed, and reduce the potential of the gate electrode by this change of potential and the capacitive coupling. Furthermore, charge sharing is carried out by connecting two gate electrodes, and the voltage of the gate electrode is reduced by capacitive coupling with another gate electrode adjacent thereto, to largely reduce the potential of the gate electrode. Thereby, the voltage level generated by the charge pump circuit can be reduced. As a result, the size of the charge pump circuit can be reduced, or the circuit itself can be eliminated, resulting in reduction of the chip area.
摘要翻译： 提供非易失性半导体存储器件。 构成存储单元的栅电极变为浮置状态，并且与其相邻的栅电极的电位改变，并且通过电位和电容耦合的这种改变来降低栅电极的电位。 此外，通过连接两个栅电极进行电荷共享，并且通过与与其相邻的另一个栅电极的电容耦合来减小栅电极的电压，从而大大减小栅电极的电位。 由此，可以降低由电荷泵电路产生的电压电平。 结果，可以减小电荷泵电路的尺寸，或者可以消除电路本身，从而减少芯片面积。
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公开(公告)号：US20080073705A1
公开(公告)日：2008-03-27
申请号：US11829248
申请日：2007-07-27
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0425 , G11C16/10 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A gate dielectric functioning as a charge-trapping layer of a non-volatile memory cell with a structure of an insulator gate field effect transistor is formed by laminating a first insulator formed of a silicon oxide film, a second insulator formed of a silicon nitride film, a third insulator formed of a silicon nitride film containing oxygen, and a fourth insulator formed of a silicon oxide film in this order on a main surface of a semiconductor substrate. Holes are injected into the charge-trapping layer from a gate electrode side. Accordingly, since the operations can be achieved without the penetration of the holes through the interface in contact to the channel and the first insulator, the deterioration in rewriting endurance and the charge-trapping characteristics due to the deterioration of the first insulator does not occur, and highly efficient rewriting (writing and erasing) characteristics and stable charge-trapping characteristics can be achieved.
摘要翻译： 作为具有绝缘体栅极场效应晶体管的结构的非易失性存储单元的电荷捕获层的栅极介质通过层叠由氧化硅膜形成的第一绝缘体，由氮化硅膜形成的第二绝缘体 由半导体衬底的主表面依次由含有氧的氮化硅膜构成的第三绝缘体和由氧化硅膜形成的第四绝缘体构成。 孔从栅电极侧注入电荷捕获层。 因此，由于可以在没有孔穿过与沟道和第一绝缘体接触的界面的情况下实现操作，所以不会发生由于第一绝缘体的劣化导致的重写耐久性和电荷捕获特性的劣化， 并且可以实现高效的重写（写入和擦除）特性和稳定的电荷捕获特性。
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