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公开(公告)号：US20080025107A1
公开(公告)日：2008-01-31
申请号：US11822120
申请日：2007-07-02
CPC分类号： G11C16/0416 , G11C16/0425 , G11C16/0433 , G11C16/0458 , G11C16/0491 , G11C16/3427 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/11568
摘要： A highly-reliable semiconductor device is realized. For example, each memory cell of a nonvolatile memory included in the semiconductor device is configured to include a source and a drain formed in a P-well, a memory node which is formed on the P-well between the source and the drain via a tunnel insulator and is insulated from its periphery, and a control gate formed on the memory node via an interlayer insulator. When a programming operation using channel hot electrons is to be performed in such a configuration, the P-well is put into an electrically floating state.
摘要翻译： 实现了高可靠性的半导体器件。 例如，包括在半导体器件中的非易失性存储器的每个存储单元被配置为包括形成在P阱中的源极和漏极，存储器节点，其通过经由一个或多个源极和漏极形成在源极和漏极之间的P阱上 隧道绝缘子，并与其周边绝缘，以及通过层间绝缘体形成在存储节点上的控制栅极。 当以这种结构执行使用通道热电子的编程操作时，P阱被置于电浮置状态。
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2.发明授权公开(公告)号：US08409949B2
公开(公告)日：2013-04-02
申请号：US12822157
申请日：2010-06-23
IPC分类号： H01L21/336
CPC分类号： H01L29/42328 , G11C16/3418 , H01L27/11521 , H01L27/1203 , H01L29/7883
摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).
摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。
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公开(公告)号：US08044455B2
公开(公告)日：2011-10-25
申请号：US12683935
申请日：2010-01-07
申请人： Yutaka Okuyama , Tsuyoshi Arigane
发明人： Yutaka Okuyama , Tsuyoshi Arigane
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L27/11529 , H01L27/11565 , H01L27/11568
摘要： A step is provided between a substrate surface of a select gate and a substrate surface of a memory gate. When the substrate surface of the select gate is lower than the substrate surface of the memory gate, electrons in a channel upon writing obliquely flow in the step portion. Even if the electrons obtain the energy required for passing a barrier during the oblique flow, the electron injection does not occur because electrons are away from the substrate surface. The injection can occur only on a drain region side from a position where the electrons reach the substrate surface. As a result, the injection of the electrons into a gap region is suppressed, so that the electron distribution comes close to the hole distribution. Therefore, variation in a threshold value upon information retention is suppressed, and information-retaining characteristics of a memory cell are improved.
摘要翻译： 在选择栅极的衬底表面和存储栅极的衬底表面之间提供一个步骤。 当选择栅极的衬底表面低于存储栅极的衬底表面时，写入中的通道中的电子在阶跃部分中倾斜地流动。 即使电子获得在斜流期间通过势垒所需的能量，电子注入也不会发生，因为电子远离衬底表面。 注入只能在电子到达基板表面的位置的漏极区域侧发生。 结果，电子注入到间隙区域被抑制，使得电子分布接近孔分布。 因此，抑制信息保持时的阈值的变化，提高存储单元的信息保持特性。
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公开(公告)号：US20100193856A1
公开(公告)日：2010-08-05
申请号：US12683935
申请日：2010-01-07
申请人： Yutaka Okuyama , Tsuyoshi Arigane
发明人： Yutaka Okuyama , Tsuyoshi Arigane
IPC分类号： H01L27/115 , H01L21/8246
CPC分类号： H01L21/28282 , H01L27/11529 , H01L27/11565 , H01L27/11568
摘要： A step is provided between a substrate surface of a select gate and a substrate surface of a memory gate. When the substrate surface of the select gate is lower than the substrate surface of the memory gate, electrons in a channel upon writing obliquely flow in the step portion. Even if the electrons obtain the energy required for passing a barrier during the oblique flow, the electron injection does not occur because electrons are away from the substrate surface. The injection can occur only on a drain region side from a position where the electrons reach the substrate surface. As a result, the injection of the electrons into a gap region is suppressed, so that the electron distribution comes close to the hole distribution. Therefore, variation in a threshold value upon information retention is suppressed, and information-retaining characteristics of a memory cell are improved.
摘要翻译： 在选择栅极的衬底表面和存储栅极的衬底表面之间提供一个步骤。 当选择栅极的衬底表面低于存储栅极的衬底表面时，写入中的通道中的电子在阶跃部分中倾斜地流动。 即使电子获得在斜流期间通过势垒所需的能量，电子注入也不会发生，因为电子远离衬底表面。 注入只能在电子到达基板表面的位置的漏极区域侧发生。 结果，电子注入到间隙区域被抑制，使得电子分布接近孔分布。 因此，抑制信息保持时的阈值的变化，提高存储单元的信息保持特性。
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公开(公告)号：US20090273014A1
公开(公告)日：2009-11-05
申请号：US12430088
申请日：2009-04-26
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/4234 , H01L27/11568 , H01L27/11573 , H01L29/792
摘要： Each of a memory gate, a control gate, a source diffusion layer, and a drain diffusion layer is connected to a control circuit for controlling potential, and the control circuit operates so as to supply a first potential to the memory gate, a second potential to the control gate, a third potential to the drain diffusion layer, and a fourth potential to the source diffusion layer. Here, after setting the memory gate to be in a floating state by shifting a switch transistor from an ON state to an OFF state, the control circuit operates so as to supply a sixth potential which is higher than the second potential to the control gate to make the memory gate have a fifth potential which is higher than the first potential, thereby boosting the memory gate.
摘要翻译： 存储器栅极，控制栅极，源极扩散层和漏极扩散层中的每一个连接到用于控制电位的控制电路，并且控制电路工作以向存储栅极提供第一电位，第二电位 到所述控制栅极，到所述漏极扩散层的第三电位，以及到所述源极扩散层的第四电位。 这里，通过将开关晶体管从导通状态切换到断开状态，在将存储栅极设定为浮置状态之后，控制电路动作以向控制栅极提供比第二电位高的第六电位， 使存储器栅极具有高于第一电位的第五电位，从而提高存储器栅极。
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公开(公告)号：US20090050956A1
公开(公告)日：2009-02-26
申请号：US12191958
申请日：2008-08-14
申请人： TETSUYA ISHIMARU , YOSHIYUKI KAWASHIMA , YASUHIRO SHIMAMOTO , KAN YASUI , TSUYOSHI ARIGANE , TOSHIYUKI MINE
发明人： TETSUYA ISHIMARU , YOSHIYUKI KAWASHIMA , YASUHIRO SHIMAMOTO , KAN YASUI , TSUYOSHI ARIGANE , TOSHIYUKI MINE
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： In a memory cell including an nMIS for memory formed on the sides of an nMIS for select and an nMIS for select via dielectric films and a charge storage layer, the thickness of a gate dielectric under the gate longitudinal direction end of a select gate electrode is formed thicker than that of the gate dielectric under the gate longitudinal direction center and the thickness of the lower layer dielectric film that is positioned between the select gate electrode and the charge storage layer and is nearest to a semiconductor substrate is formed 1.5 times or below of the thickness of the lower layer dielectric film positioned between the semiconductor substrate and the charge storage layer.
摘要翻译： 在包括形成在用于选择的nMIS的侧面上的存储器的nMIS和通过电介质膜和电荷存储层进行选择的nMIS的存储单元中，选择栅电极的栅极纵向端的栅极电介质的厚度为 在栅极纵向中心处形成得比栅极电介质厚，并且位于选择栅电极和电荷存储层之间并且最靠近半导体衬底的下层电介质膜的厚度形成为1.5倍以下 位于半导体衬底和电荷存储层之间的下层电介质膜的厚度。
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7.发明申请Non-volatile semiconductor storage device and the manufacturing method thereof 审中-公开非易失性半导体存储装置及其制造方法公开(公告)号：US20060183284A1
公开(公告)日：2006-08-17
申请号：US11316817
申请日：2005-12-27
IPC分类号： H01L21/336
CPC分类号： G11C16/0491 , G11C16/0433 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/40114
摘要： High integration and making a non-volatile semiconductor memory efficient have been promoted. The memory cell consists of a floating gate, a control gate constituting a word line WL and a MOS transistor having an assist gate. The thickness of the gate oxide film of the assist gate is thinner than the thickness of the gate oxide layer of the floating gate, and the dimensions of the assist gate (gate width) in the direction lying along the word line WL is smaller than the gate length of the floating gate in the direction lying along the word line WL. Moreover, the channel dopant concentration underneath the assist gate is lower than the channel dopant concentration underneath the floating gate.
摘要翻译： 高集成度和非易失性半导体存储器的高效率得到了提升。 存储单元包括浮置栅极，构成字线WL的控制栅极和具有辅助栅极的MOS晶体管。 辅助栅极的栅极氧化膜的厚度比浮栅的栅极氧化物层的厚度薄，并且沿着字线WL的方向上的辅助栅极（栅极宽度）的尺寸小于 浮栅的沿着字线WL的方向的栅极长度。 此外，辅助栅极下方的沟道掺杂剂浓度低于浮栅下方的沟道掺杂剂浓度。
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公开(公告)号：US20110235419A1
公开(公告)日：2011-09-29
申请号：US13073988
申请日：2011-03-28
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0466 , G11C16/14 , G11C16/30 , H01L27/11563 , H01L29/42344
摘要： In a split gate MONOS memory which carries out rewrite by hot carrier injection, retention characteristics are improved. A select gate electrode of a memory cell is connected to a select gate line, and a memory gate electrode is connected to a memory gate line. A drain region is connected to a bit line, and a source region is connected to a source line. Furthermore, a well line is connected to a p type well region in which the memory cell is formed. When write to the memory cell is to be carried out, write by a source side injection method is carried out while applying a negative voltage to the p type well region via the well line.
摘要翻译： 在通过热载流子注入进行重写的分闸门MONOS存储器中，保持特性得到改善。 存储单元的选择栅电极连接到选择栅极线，并且存储栅电极连接到存储栅极线。 漏极区域连接到位线，并且源极区域连接到源极线。 此外，阱线连接到其中形成存储单元的p型阱区域。 当要对存储单元进行写入时，通过源极侧注入方法进行写入，同时通过阱线向p型阱区域施加负电压。
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公开(公告)号：US07471563B2
公开(公告)日：2008-12-30
申请号：US11652023
申请日：2007-01-11
IPC分类号： G11C11/34
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0433 , G11C16/12 , G11C16/3459 , H01L27/115 , H01L27/11524
摘要： Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.
摘要翻译： 在闪速存储器中需要抑制泄漏电流，因为随着存储器单元尺寸的减小，通道长度变短。 在具有辅助电极的AND型存储器阵列中，虽然通过使用MOS晶体管的场隔离来减小存储单元面积，但是由于存储单元尺寸的减小，沟道方向的泄漏电流变大，导致出现像 编程特性恶化，电流消耗增加，读取失败。 为了实现该目的，在本发明中，通过在编程和读取操作期间将辅助电极并联布置的至少一个辅助电极作为负电压进行电隔离，并且通过使半导体衬底表面在 上述辅助电极不导电。
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公开(公告)号：US07468913B2
公开(公告)日：2008-12-23
申请号：US11822120
申请日：2007-07-02
IPC分类号： G11C16/00
CPC分类号： G11C16/0416 , G11C16/0425 , G11C16/0433 , G11C16/0458 , G11C16/0491 , G11C16/3427 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/11568
摘要： A highly-reliable semiconductor device is realized. For example, each memory cell of a nonvolatile memory included in the semiconductor device is configured to include a source and a drain formed in a P-well, a memory node which is formed on the P-well between the source and the drain via a tunnel insulator and is insulated from its periphery, and a control gate formed on the memory node via an interlayer insulator. When a programming operation using channel hot electrons is to be performed in such a configuration, the P-well is put into an electrically floating state.
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