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公开(公告)号：US20150179744A1
公开(公告)日：2015-06-25
申请号：US14413435
申请日：2012-07-09
IPC分类号： H01L29/16 , H01L29/51 , H01L29/423 , H01L29/78 , H01L29/10
CPC分类号： H01L29/1608 , H01L29/0657 , H01L29/1079 , H01L29/12 , H01L29/4236 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/66068 , H01L29/78 , H01L29/7802 , H01L29/7813 , H01L29/7926
摘要： The present invention is to cause high channel mobility and a high threshold voltage to coexist in a SiC-MOSFET power device which uses a SiC substrate. The SiC MOSFET which is provided with a layered insulation film having electric charge trap characteristics on a gate insulation film has an irregular threshold voltage in a channel length direction of the SiC MOSFET, and in particular, has a shorter area having a maximum threshold voltage in the channel length direction compared to an area having other threshold voltages.
摘要翻译： 本发明是在使用SiC衬底的SiC-MOSFET功率器件中使高通道迁移率和高阈值电压共存。 在栅极绝缘膜上具有电荷陷阱特性的分层绝缘膜的SiC MOSFET在SiC MOSFET的沟道长度方向上具有不规则的阈值电压，特别是具有最小阈值电压的较短区域 通道长度方向与具有其它阈值电压的区域相比较。
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2.发明授权公开(公告)号：US08409949B2
公开(公告)日：2013-04-02
申请号：US12822157
申请日：2010-06-23
IPC分类号： H01L21/336
CPC分类号： H01L29/42328 , G11C16/3418 , H01L27/11521 , H01L27/1203 , H01L29/7883
摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).
摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。
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公开(公告)号：US07935597B2
公开(公告)日：2011-05-03
申请号：US12912609
申请日：2010-10-26
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , G11C16/0425 , H01L21/28282 , H01L21/31155 , H01L27/105 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/42344 , H01L29/66833
摘要： Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.
摘要翻译： 提高了包括非易失性存储器的半导体器件的性能和可靠性。 非易失性存储器的存储单元包括在半导体衬底的上部上的经由第一电介质膜形成的选择栅电极和通过由具有电荷的ONO多层膜形成的第二电介质膜形成的存储栅电极 存储功能。 第一电介质膜用作栅极电介质膜，并且包括由氧化硅或氮氧化硅制成的第三电介质膜和由选择栅电极和第三电极之间形成的金属氧化物或金属硅酸盐构成的含金属元素层 电介质膜。 位于存储栅电极下方的半导体区域和第二电介质膜的电荷密度低于位于选择栅电极和第一电介质膜下方的半导体区域的电荷密度。
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公开(公告)号：US07915686B2
公开(公告)日：2011-03-29
申请号：US11439260
申请日：2006-05-24
IPC分类号： H01L29/76
CPC分类号： H01L27/092 , H01L21/28035 , H01L21/28202 , H01L21/28229 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823857 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： An object of the present invention is to improve the performance of a semiconductor device having a CMISFET. Each of an n channel MISFET and a p channel MISFET which form the CMISFET includes a gate insulating film composed of a silicon oxynitride film and a gate electrode including a silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film with a surface density of 1×1013 to 5×1014 atoms/cm2. The impurity concentration of channel regions of the n channel MISFET and the p channel MISFET is controlled to be equal to or lower than 1.2×1018/cm3.
摘要翻译： 本发明的目的是提高具有CMISFET的半导体器件的性能。 形成CMISFET的n沟道MISFET和p沟道MISFET中的每一个包括由氮氧化硅膜和包括位于栅极绝缘膜上的硅膜的栅电极构成的栅极绝缘膜。 诸如Hf之类的金属元素以1×1013至5×1014原子/ cm2的表面密度引入栅电极和栅绝缘膜之间的界面附近。 n沟道MISFET和p沟道MISFET的沟道区域的杂质浓度被控制在等于或低于1.2×1018 / cm3。
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公开(公告)号：US20090273014A1
公开(公告)日：2009-11-05
申请号：US12430088
申请日：2009-04-26
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/4234 , H01L27/11568 , H01L27/11573 , H01L29/792
摘要： Each of a memory gate, a control gate, a source diffusion layer, and a drain diffusion layer is connected to a control circuit for controlling potential, and the control circuit operates so as to supply a first potential to the memory gate, a second potential to the control gate, a third potential to the drain diffusion layer, and a fourth potential to the source diffusion layer. Here, after setting the memory gate to be in a floating state by shifting a switch transistor from an ON state to an OFF state, the control circuit operates so as to supply a sixth potential which is higher than the second potential to the control gate to make the memory gate have a fifth potential which is higher than the first potential, thereby boosting the memory gate.
摘要翻译： 存储器栅极，控制栅极，源极扩散层和漏极扩散层中的每一个连接到用于控制电位的控制电路，并且控制电路工作以向存储栅极提供第一电位，第二电位 到所述控制栅极，到所述漏极扩散层的第三电位，以及到所述源极扩散层的第四电位。 这里，通过将开关晶体管从导通状态切换到断开状态，在将存储栅极设定为浮置状态之后，控制电路动作以向控制栅极提供比第二电位高的第六电位， 使存储器栅极具有高于第一电位的第五电位，从而提高存储器栅极。
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公开(公告)号：US20090050956A1
公开(公告)日：2009-02-26
申请号：US12191958
申请日：2008-08-14
申请人： TETSUYA ISHIMARU , YOSHIYUKI KAWASHIMA , YASUHIRO SHIMAMOTO , KAN YASUI , TSUYOSHI ARIGANE , TOSHIYUKI MINE
发明人： TETSUYA ISHIMARU , YOSHIYUKI KAWASHIMA , YASUHIRO SHIMAMOTO , KAN YASUI , TSUYOSHI ARIGANE , TOSHIYUKI MINE
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： In a memory cell including an nMIS for memory formed on the sides of an nMIS for select and an nMIS for select via dielectric films and a charge storage layer, the thickness of a gate dielectric under the gate longitudinal direction end of a select gate electrode is formed thicker than that of the gate dielectric under the gate longitudinal direction center and the thickness of the lower layer dielectric film that is positioned between the select gate electrode and the charge storage layer and is nearest to a semiconductor substrate is formed 1.5 times or below of the thickness of the lower layer dielectric film positioned between the semiconductor substrate and the charge storage layer.
摘要翻译： 在包括形成在用于选择的nMIS的侧面上的存储器的nMIS和通过电介质膜和电荷存储层进行选择的nMIS的存储单元中，选择栅电极的栅极纵向端的栅极电介质的厚度为 在栅极纵向中心处形成得比栅极电介质厚，并且位于选择栅电极和电荷存储层之间并且最靠近半导体衬底的下层电介质膜的厚度形成为1.5倍以下 位于半导体衬底和电荷存储层之间的下层电介质膜的厚度。
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公开(公告)号：US20080290401A1
公开(公告)日：2008-11-27
申请号：US12124143
申请日：2008-05-20
申请人： Kan YASUI , Tetsuya Ishimaru , Digh Hisamoto , Yasuhiro Shimamoto
发明人： Kan YASUI , Tetsuya Ishimaru , Digh Hisamoto , Yasuhiro Shimamoto
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0425 , G11C16/10 , H01L27/11526 , H01L27/11546 , H01L29/42344
摘要： An erase method where a corner portion on which an electric field concentrates locally is provided on the memory gate electrode, and charges in the memory gate electrode are injected into a charge trap film in a gate dielectric with Fowler-Nordheim tunneling operation is used. Since current consumption at the time of erase can be reduced by the Fowler-Nordheim tunneling, a power supply circuit area of a memory module can be reduced. Since write disturb resistance can be improved, a memory array area can be reduced by adopting a simpler memory array configuration. Owing to both the effects, an area of the memory module can be largely reduced, so that manufacturing cost can be reduced. Further, since charge injection centers of write and erase coincide with each other, so that (program and erase) endurance is improved.
摘要翻译： 在存储栅电极上设置有局部集中电场的角部的擦除方法，并且使用Fowler-Nordheim隧道操作将存储栅电极中的电荷注入栅极电介质中的电荷陷阱膜。 由于通过Fowler-Nordheim隧道可以减少擦除时的电流消耗，因此可以减少存储器模块的电源电路区域。 由于可以提高写入干扰电阻，所以可以通过采用更简单的存储器阵列配置来减少存储器阵列区域。 由于这两个效果，可以大大减少存储器模块的面积，从而可以降低制造成本。 此外，由于写入和擦除的电荷注入中心彼此一致，所以（编程和擦除）耐久性得到改善。
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公开(公告)号：US07112833B2
公开(公告)日：2006-09-26
申请号：US10788278
申请日：2004-03-01
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L21/28202 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6659
摘要： The technique capable of reducing the power consumption in the MISFET by suppressing the scattering of the carriers due to the fixed charges is provided. A silicon oxynitride film with a physical thickness of 1.5 nm or more and the relative dielectric constant of 4.1 or higher is formed at the interface between a semiconductor substrate and an alumina film. By so doing, a gate insulator composed of the silicon oxynitride film and the alumina film is constituted. The silicon oxynitride film is formed by performing a thermal treatment of a silicon oxide film formed on the semiconductor substrate in a NO or N2O atmosphere. In this manner, the fixed charges in the silicon oxynitride film are set to 5×1012 cm−2 or less, and the fixed charges in the interface between the silicon oxynitride film and the alumina film are set to 5×1012 cm−2 or more.
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9.发明申请Semiconductor device with gate insulating film and manufacturing method thereof 审中-公开具有栅极绝缘膜的半导体器件及其制造方法公开(公告)号：US20060208325A1
公开(公告)日：2006-09-21
申请号：US11373112
申请日：2006-03-13
申请人： Masaharu Mizutani , Masao Inoue , Jiro Yugami , Junichi Tsuchimoto , Koji Nomura , Yasuhiro Shimamoto
发明人： Masaharu Mizutani , Masao Inoue , Jiro Yugami , Junichi Tsuchimoto , Koji Nomura , Yasuhiro Shimamoto
IPC分类号： H01L29/94
CPC分类号： H01L29/7833 , H01L29/1083 , H01L29/6659
摘要： A MISFET includes: a p type substrate having a channel region with an impurity concentration C; an insulating film made of SiO2 and formed on the channel region; and an insulating film made of HfSiON and formed on the gate insulating film. When there is a postulated MISFET including a postulated substrate having a channel region with the impurity concentration C and made of a material identical to the substrate and an insulating film made solely of SiON formed on the channel region, said impurity concentration C of channel region is set so that a maximum value of mobility of electrons in said channel region is higher than a maximum value of mobility of electrons in the postulated channel region. Thus, the power supply voltage can be reduced and the power consumption can be reduced.
摘要翻译： MISFET包括：具有杂质浓度C的沟道区的p型衬底; 形成在沟道区上的由SiO 2构成的绝缘膜; 以及由栅极绝缘膜形成的由HfSiON构成的绝缘膜。 当存在假设的MISFET，其包括具有杂质浓度C并且由与衬底相同的材料制成的沟道区域和由沟道区域上形成的仅由SiON制成的绝缘膜的假定衬底时，沟道区的杂质浓度C 使得所述沟道区中的电子的迁移率的最大值高于假定沟道区中的电子的迁移率的最大值。 因此，可以降低电源电压并且可以降低功耗。
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公开(公告)号：US06509246B2
公开(公告)日：2003-01-21
申请号：US09877207
申请日：2001-06-11
IPC分类号： H01L2120
CPC分类号： H01L28/84 , H01L27/10814 , H01L28/91
摘要： A semiconductor integrated circuit in which the storage capacitor has an increased capacitance and a decreased leakage current. The storage capacitor is formed by the steps of: forming a polysilicon bottom electrode having semispherical silicon crystals formed thereon; performing plasma nitriding on the surface of said bottom electrode at a temperature lower than 550° C., thereby forming a film of silicon nitride having a film thickness smaller than 1.5 nm; and depositing a film of amorphous tantalum pentoxide and then crystallizing said amorphous tantalum pentoxide. The silicon nitride film has improved resistance to oxidation and also has a reduced leakage current. As a result, the polysilicon bottom electrode becomes resistant to oxidation and the storage capacitor increases in capacitance and decreases in leakage current.
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