公开(公告)号：US20240397689A1

公开(公告)日：2024-11-28

申请号：US18337434

申请日：2023-06-20

Applicant: United Microelectronics Corp.

Inventor： Hsin-Hsien Chen ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang ,  Kuo-Hsing Lee

IPC: H10B10/00

Abstract: A static random access memory (SRAM) includes a first memory cell. The first memory cell includes: a first pull-down transistor, a first pull-up transistor, a second pull-up transistor, and a second pull-down transistor arranged on a first segment of a first fin, a first segment of a second fin, a first segment of a third fin and a first segment of a fourth fin of a substrate, respectively. The first memory cell further includes a first diode and a second diode. The first diode includes a first conductive feature in contact with a top surface and multiple upper sidewalls of a first end of the first segment of the first fin. The second diode includes a second conductive feature in contact with a top surface and multiple upper sidewalls of a second end of the first segment of the fourth fin.

公开(公告)号：US20230422491A1

公开(公告)日：2023-12-28

申请号：US17869752

申请日：2022-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Chen Chiu ,  Chi-Horn Pai ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H01L27/112

CPC classification number: H01L27/11206

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, removing part of the STI to form a first step on a corner of the substrate, forming a first gate oxide layer on the substrate, removing the first gate oxide layer to form a second step on the corner of the substrate, forming a second gate oxide layer on the substrate, and then forming a first gate structure on the substrate and the STI.

公开(公告)号：US20230380148A1

公开(公告)日：2023-11-23

申请号：US17844076

申请日：2022-06-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Chih-Kai Kang ,  Ting-Hsiang Huang ,  Chien-Liang Wu ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai

IPC: H01L27/112

CPC classification number: H01L27/11206

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, forming a first doped region adjacent to the STI, removing part of the STI, and then forming a first gate structure on the substrate and the STI. Preferably, the first gate structure includes a high-k dielectric layer on the substrate and a gate electrode on the high-k dielectric layer, in which the high-k dielectric layer comprises a first L-shape.

公开(公告)号：US11532666B2

公开(公告)日：2022-12-20

申请号：US17207728

申请日：2021-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Hsiang Huang ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle, a top view of the first metal interconnection includes a flat oval overlapping the circle, and the MTJ includes a bottom electrode, a fixed layer, a free layer, a capping layer, and a top electrode.

公开(公告)号：US10692928B1

公开(公告)日：2020-06-23

申请号：US16260129

申请日：2019-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Hsiang Huang ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H01L27/22 ,  H01L29/66 ,  H01L43/12 ,  H01L43/08 ,  H01L29/08 ,  H01L29/49 ,  H01L43/02

Abstract: A semiconductor device includes: a dummy gate on a substrate; a first control gate on one side of the dummy gate and a second control gate on another side of the dummy gate; a well in the substrate, wherein the well comprises a first conductive type; a first source/drain region between the dummy gate and the first control gate, wherein the first source/drain region comprises a second conductive type; a second source/drain region between the dummy gate and the second control gate, wherein the second source/drain region comprises the second conductive type; and a doped region directly under the dummy gate, wherein the doped region comprises the first conductive type.

公开(公告)号：US20200091229A1

公开(公告)日：2020-03-19

申请号：US16167485

申请日：2018-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Hsiang Huang ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/08

Abstract: A magnetic random access memory (MRAM) includes device strings coupled in parallel, each comprising magnetic tunnel junctions (MTJs) coupled in serial, wherein a quantity of the MTJs of each of the device strings is equal to a quantity of the device strings, and an equivalent resistance (Req) of the MTJs is equal to an average of the sum of a high resistance of one of the MTJs and a low resistance of another MTJ.

公开(公告)号：US20250107101A1

公开(公告)日：2025-03-27

申请号：US18974816

申请日：2024-12-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Hsiang Huang ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H10B61/00 ,  H10N50/10 ,  H10N50/80

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

公开(公告)号：US12261169B2

公开(公告)日：2025-03-25

申请号：US17732570

申请日：2022-04-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang ,  Chun-Hsien Lin ,  Chi-Horn Pai

IPC: H01L27/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

公开(公告)号：US20240130140A1

公开(公告)日：2024-04-18

申请号：US18395762

申请日：2023-12-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Hsiang Huang ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H10B61/00 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10B61/10 ,  H10N50/10 ,  H10N50/80

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

公开(公告)号：US11296214B2

公开(公告)日：2022-04-05

申请号：US16525513

申请日：2019-07-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang ,  Guan-Kai Huang ,  Chien-Liang Wu

IPC: H01L29/778 ,  H01L29/66

Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).