公开(公告)号：US20170162450A1

公开(公告)日：2017-06-08

申请号：US15435280

申请日：2017-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Duan Quan Liao ,  Yikun Chen ,  Ching-Hwa Tey ,  Xiao Zhong Zhu

IPC: H01L21/8238 ,  H01L23/535 ,  H01L29/08 ,  H01L29/161 ,  H01L27/11 ,  H01L29/78 ,  H01L21/285 ,  H01L21/768 ,  H01L29/66 ,  H01L27/092 ,  H01L29/16

CPC classification number: H01L21/823871 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor structure includes at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source/drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source/drain region. Additionally, a semiconductor process formed said semiconductor structure is also provided.

公开(公告)号：US20250031585A1

公开(公告)日：2025-01-23

申请号：US18447317

申请日：2023-08-10

Applicant: United Microelectronics Corp.

Inventor： Zhaoyao Zhan ,  Jian Shi ,  Xiaohong Jiang ,  Ching-Hwa Tey

IPC: H10N70/00 ,  H10B63/00

Abstract: A resistive random access memory includes a first electrode, a second electrode, a dielectric layer, a protection layer, and at least one switching layer. The dielectric layer is formed on the first electrode. The dielectric layer has an opening exposing a portion of the first electrode. The protection layer is disposed on sidewalls of the opening. The switching layer is disposed on the exposed portion of the first electrode and exposes a portion of sidewalls of the protection layer. The second electrode is at least one conductive layer and is disposed on the switching layer in the opening.

公开(公告)号：US20250022905A1

公开(公告)日：2025-01-16

申请号：US18900947

申请日：2024-09-30

Applicant: United Microelectronics Corp.

Inventor： Zhaoyao Zhan ,  Jing Feng ,  Qianwei Ding ,  Xiaohong Jiang ,  Ching-Hwa Tey

IPC: H01L27/146

Abstract: An image sensor structure including a substrate, a nanowire structure, a first conductive line, a second conductive line, and a third conductive line is provided. The nanowire structure includes a first doped layer, a second doped layer, a third doped layer, and a fourth doped layer sequentially stacked on the substrate. The first doped layer and the third doped layer have a first conductive type. The second doped layer and the fourth doped layer have a second conductive type. The first conductive line is connected to a sidewall of the second doped layer. The second conductive line is connected to a sidewall of the third doped layer. The third conductive line is connected to the fourth doped layer.

公开(公告)号：US20180197819A1

公开(公告)日：2018-07-12

申请号：US15400600

申请日：2017-01-06

Applicant: United Microelectronics Corp.

Inventor： Keen Zhang ,  Ji Feng ,  De-Jin Kong ,  Yun-Fei Li ,  Guo-Hai Zhang ,  Ching-Hwa Tey ,  Jing Feng

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L23/53295 ,  H01L23/5283 ,  H01L23/53228

Abstract: An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one UTM layer is disposed on the substrate. The first dielectric layer is disposed on the at least one UTM layer and exposes the at least one UTM layer. A stress of the first dielectric layer is −150 Mpa to −500 Mpa. The at least one pad metal layer is disposed on the first dielectric layer and electrically connected to the at least one UTM layer exposed by the first dielectric layer.

公开(公告)号：US12176375B2

公开(公告)日：2024-12-24

申请号：US17322599

申请日：2021-05-17

Applicant: United Microelectronics Corp.

Inventor： Zhaoyao Zhan ,  Jing Feng ,  Qianwei Ding ,  Xiaohong Jiang ,  Ching-Hwa Tey

IPC: H01L27/146

Abstract: An image sensor structure including a substrate, a nanowire structure, a first conductive line, a second conductive line, and a third conductive line is provided. The nanowire structure includes a first doped layer, a second doped layer, a third doped layer, and a fourth doped layer sequentially stacked on the substrate. The first doped layer and the third doped layer have a first conductive type. The second doped layer and the fourth doped layer have a second conductive type. The first conductive line is connected to a sidewall of the second doped layer. The second conductive line is connected to a sidewall of the third doped layer. The third conductive line is connected to the fourth doped layer.

公开(公告)号：US12094758B2

公开(公告)日：2024-09-17

申请号：US17843089

申请日：2022-06-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Tsai Hung ,  Yi Liu ,  Guo-Hai Zhang ,  Ching-Hwa Tey

IPC: H01L21/762 ,  H01L23/00 ,  H01L27/12

CPC classification number: H01L21/76251 ,  H01L23/562 ,  H01L23/564 ,  H01L27/1203

Abstract: A semiconductor structure is provided. The semiconductor structure includes a wafer structure. The wafer structure has a normal region and a trimmed region adjacent to the normal region. A top surface of the trimmed region is lower than a top surface of the normal region. The semiconductor structure includes a dielectric layer and a conductive layer disposed on the wafer structure in the normal region and the trimmed region. The semiconductor structure includes a protective layer disposed on a portion of the dielectric layer in the trimmed region and a portion of the conductive layer in the trimmed region. The semiconductor structure includes another dielectric layer disposed on a portion of the dielectric layer in the normal region and a portion of the conductive layer in the normal region and on the protective layer.

公开(公告)号：US11527605B2

公开(公告)日：2022-12-13

申请号：US17364935

申请日：2021-07-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Ji Chen ,  Jing Feng ,  Xiao-Hong Jiang ,  Ching-Hwa Tey

IPC: H01L49/02 ,  H01L21/66 ,  H01L23/522 ,  H01L21/67 ,  G01R27/26 ,  G01R31/26

Abstract: A method for fabricating a MOMCAP includes steps as follows: An Nth metal layer is formed on a substrate according to an Nth expected capacitance value of the Nth metal layer. An Nth capacitance error value between an Nth actual capacitance value of the Nth metal layer and the Nth expected capacitance value is calculated. An N+1th expected capacitance value of an N+1th metal layer is adjusted to form an N+1th actual capacitance value according to the Nth capacitance error value, and the N+1th metal layer with an N+1th actual capacitance value is formed on the Nth metal layer according to the adjusted N+1th expected capacitance value, to make the sum of the Nth actual capacitance value and the N+1th actual capacitance value equal to the sum of the Nth expected capacitance value and the N+1th expected capacitance value. N is an integer greater than 1.

公开(公告)号：US20220336519A1

公开(公告)日：2022-10-20

申请号：US17322599

申请日：2021-05-17

Applicant: United Microelectronics Corp.

Inventor： Zhaoyao Zhan ,  Jing Feng ,  Qianwei Ding ,  Xiaohong Jiang ,  Ching-Hwa Tey

IPC: H01L27/146

Abstract: An image sensor structure including a substrate, a nanowire structure, a first conductive line, a second conductive line, and a third conductive line is provided. The nanowire structure includes a first doped layer, a second doped layer, a third doped layer, and a fourth doped layer sequentially stacked on the substrate. The first doped layer and the third doped layer have a first conductive type. The second doped layer and the fourth doped layer have a second conductive type. The first conductive line is connected to a sidewall of the second doped layer. The second conductive line is connected to a sidewall of the third doped layer. The third conductive line is connected to the fourth doped layer.

公开(公告)号：US10332839B2

公开(公告)日：2019-06-25

申请号：US15400600

申请日：2017-01-06

Applicant: United Microelectronics Corp.

Inventor： Keen Zhang ,  Ji Feng ,  De-Jin Kong ,  Yun-Fei Li ,  Guo-Hai Zhang ,  Ching-Hwa Tey ,  Jing Feng

IPC: H01L21/00 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

Abstract: An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one UTM layer is disposed on the substrate. The first dielectric layer is disposed on the at least one UTM layer and exposes the at least one UTM layer. A stress of the first dielectric layer is −150 Mpa to −500 Mpa. The at least one pad metal layer is disposed on the first dielectric layer and electrically connected to the at least one UTM layer exposed by the first dielectric layer.