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公开(公告)号：US09783408B2
公开(公告)日：2017-10-10
申请号：US14307512
申请日：2014-06-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Bang-Chiang Lan , Ming-I Wang , Li-Hsun Ho , Hui-Min Wu , Min Chen , Chien-Hsin Huang
CPC classification number: B81B3/0021 , B81B2201/0271 , H04R3/00 , H04R7/00 , H04R19/005 , H04R31/00 , H04R2499/11 , Y10T29/49002
Abstract: A structure of micro-electro-mechanical systems (MEMS) electroacoustic transducer is disclosed. The MEMS electroacoustic transducer includes a substrate having a MEMS device region, a diaphragm having openings and disposed in the MEMS device region, a silicon material layer disposed on the diaphragm and sealing the diaphragm, and a conductive pattern disposed beneath the diaphragm in the MEMS device region. Preferably, a first cavity is also formed between the diaphragm and the substrate.
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2.发明申请METHOD OF FABRICATING INTEGRATED STRUCTURE FOR MEMS DEVICE AND SEMICONDUCTOR DEVICE 有权制造MEMS器件和半导体器件的集成结构的方法公开(公告)号：US20150004732A1
公开(公告)日：2015-01-01
申请号：US14489495
申请日：2014-09-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Bang-Chiang Lan , Li-Hsun Ho , Wei-Cheng Wu , Hui-Min Wu , Min Chen , Tzung-I Su , Chien-Hsin Huang
IPC: B81C1/00
CPC classification number: B81C1/00246 , B81C1/00801 , B81C2201/014 , B81C2203/0714 , B81C2203/0742 , B81C2203/0792 , H01L27/0688
Abstract: A method of fabricating an integrated structure for MEMS device and semiconductor device comprises steps of: providing a substrate having a transistor thereon in a semiconductor device region and a first MEMS component thereon in a MEMS region; performing a interconnect process on the substrate in the semiconductor device region to form a plurality of first dielectric layers, at least a conductive plug and at least a conductive layer in the first dielectric layers; forming a plurality of second dielectric layers and an etch stopping device in the second dielectric layers on the substrate in a etch stopping device region; forming a plurality of third dielectric layers and at least a second MEMS component in the third dielectric layers on the substrate in the MEMS region; and performing an etching process to remove the third dielectric layers in the MEMS region.
Abstract translation: 制造用于MEMS器件和半导体器件的集成结构的方法包括以下步骤：在半导体器件区域中提供其上具有晶体管的衬底及其中的MEMS区域中的第一MEMS部件; 在所述半导体器件区域中的所述衬底上执行互连处理，以形成多个第一电介质层，所述第一介电层中的至少导电插塞和至少导电层; 在蚀刻停止装置区域中在衬底上的第二介电层中形成多个第二电介质层和蚀刻停止装置; 在MEMS区域中的衬底上的第三电介质层中形成多个第三电介质层和至少第二MEMS部件; 并执行蚀刻工艺以去除MEMS区域中的第三介电层。
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公开(公告)号：US20140291787A1
公开(公告)日：2014-10-02
申请号：US14307512
申请日：2014-06-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Bang-Chiang Lan , Ming-I Wang , Li-Hsun Ho , Hui-Min Wu , Min Chen , Chien-Hsin Huang
CPC classification number: B81B3/0021 , B81B2201/0271 , H04R3/00 , H04R7/00 , H04R19/005 , H04R31/00 , H04R2499/11 , Y10T29/49002
Abstract: A structure of micro-electro-mechanical systems (MEMS) electroacoustic transducer is disclosed. The MEMS electroacoustic transducer includes a substrate having a MEMS device region, a diaphragm having openings and disposed in the MEMS device region, a silicon material layer disposed on the diaphragm and sealing the diaphragm, and a conductive pattern disposed beneath the diaphragm in the MEMS device region. Preferably, a first cavity is also formed between the diaphragm and the substrate.
Abstract translation: 公开了一种微电子机械系统（MEMS）电声换能器的结构。 MEMS电声换能器包括具有MEMS器件区域的基板，具有开口且设置在MEMS器件区域中的隔膜，设置在隔膜上并密封隔膜的硅材料层，以及设置在MEMS器件的隔膜下方的导电图案 地区。 优选地，在隔膜和基板之间也形成第一空腔。
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4.发明授权Method for forming MEMS structure with an etch stop layer buried within inter-dielectric layer 有权用埋置在介电层内的蚀刻停止层形成MEMS结构的方法公开(公告)号：US09499399B2
公开(公告)日：2016-11-22
申请号：US13917655
申请日：2013-06-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Li-Che Chen , Te-Yuan Wu , Chia-Huei Lin , Hui-Min Wu , Kun-Che Hsieh , Kuan-Yu Wang , Chung-Yi Chiu
IPC: B81C1/00 , H01L21/302 , H01L21/461
CPC classification number: B81B3/0075 , B81B2207/07 , B81C1/00246 , B81C1/00801 , B81C2201/014 , B81C2203/0714 , B81C2203/0735
Abstract: A method of forming a MEMS structure, in which an etch stop layer is formed to be buried within the inter-dielectric layer and, during an etch of the substrate and the inter-dielectric layer from backside to form a chamber, the etch stop layer protect the remaining inter-dielectric layer. The chamber thus formed has an opening at a backside of the substrate, a ceiling opposite to the opening, and a sidewall joining the ceiling. The sidewall may further include a portion of the etch stop layer.
Abstract translation: 一种形成MEMS结构的方法，其中形成蚀刻停止层以埋入介电层内，并且在从背面蚀刻基板和介电层之间形成室时，蚀刻停止层 保护剩余的介电层。 如此形成的室在基板的背面具有开口，与开口相对的天花板和连接天花板的侧壁。 侧壁还可包括蚀刻停止层的一部分。
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公开(公告)号：US20150011035A1
公开(公告)日：2015-01-08
申请号：US13933135
申请日：2013-07-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kuan-Yu Wang , Hui-Min Wu , Kun-Che Hsieh
IPC: B81C1/00
CPC classification number: B81B3/0072 , B81B2201/0235 , B81B2201/0242 , B81C2203/0742
Abstract: A method for fabricating an integrated device includes the following steps. First, a multi-layered structure is formed on a substrate, wherein the multi-layered structure is embedded in a lower isolation layer. Then, a bottom conductive pattern and a top conductive pattern are formed on a top surface of the lower isolation layer, wherein the top conductive pattern is on a top surface of the bottom conductive pattern. Afterwards, portions of the top conductive pattern are removed to expose portions of the bottom conductive pattern. Subsequently, an upper isolation layer is deposited on the lower isolation layer so that the upper isolation layer can be in direct contact with the portions of the bottom conductive pattern. Finally, portions of the lower isolation layer and the upper isolation layer are removed so as to expose portions of the substrate.
Abstract translation: 一种用于制造集成装置的方法包括以下步骤。 首先，在基板上形成多层结构，其中多层结构被嵌入在下隔离层中。 然后，在下隔离层的顶表面上形成底部导电图案和顶部导电图案，其中顶部导电图案位于底部导电图案的顶表面上。 之后，顶部导电图案的部分被去除以暴露底部导电图案的部分。 随后，上隔离层沉积在下隔离层上，使得上隔离层可以与底导电图案的部分直接接触。 最后，去除下隔离层和上隔离层的部分以露出基板的部分。
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Patent Agency Ranking
公开(公告)号：US20140367805A1
公开(公告)日：2014-12-18
申请号：US13917655
申请日：2013-06-14
Applicant: United Microelectronics Corp.
Inventor： Li-Che Chen , Te-Yuan Wu , Chia-Huei Lin , Hui-Min Wu , Kun-Che Hsieh , Kuan-Yu Wang , Chung-Yi Chiu
IPC: B81C1/00
CPC classification number: B81B3/0075 , B81B2207/07 , B81C1/00246 , B81C1/00801 , B81C2201/014 , B81C2203/0714 , B81C2203/0735
Abstract: A method of forming a MEMS structure, in which an etch stop layer is formed to be buried within the inter-dielectric layer and, during an etch of the substrate and the inter-dielectric layer from backside to form a chamber, the etch stop layer protect the remaining inter-dielectric layer. The chamber thus formed has an opening at a backside of the substrate, a ceiling opposite to the opening, and a sidewall joining the ceiling. The sidewall may further include a portion of the etch stop layer.
Abstract translation: 一种形成MEMS结构的方法，其中形成蚀刻停止层以埋入介电层内，并且在从背面蚀刻基板和介电层之间形成室时，蚀刻停止层 保护剩余的介电层。 如此形成的室在基板的背面具有开口，与开口相对的天花板和连接天花板的侧壁。 侧壁还可包括蚀刻停止层的一部分。
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公开(公告)号：US09988264B2
公开(公告)日：2018-06-05
申请号：US14489495
申请日：2014-09-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Bang-Chiang Lan , Li-Hsun Ho , Wei-Cheng Wu , Hui-Min Wu , Min Chen , Tzung-I Su , Chien-Hsin Huang
CPC classification number: B81C1/00246 , B81C1/00801 , B81C2201/014 , B81C2203/0714 , B81C2203/0742 , B81C2203/0792 , H01L27/0688
Abstract: A method of fabricating an integrated structure for MEMS device and semiconductor device comprises steps of: providing a substrate having a transistor thereon in a semiconductor device region and a first MEMS component thereon in a MEMS region; performing a interconnect process on the substrate in the semiconductor device region to form a plurality of first dielectric layers, at least a conductive plug and at least a conductive layer in the first dielectric layers; forming a plurality of second dielectric layers and an etch stopping device in the second dielectric layers on the substrate in a etch stopping device region; forming a plurality of third dielectric layers and at least a second MEMS component in the third dielectric layers on the substrate in the MEMS region; and performing an etching process to remove the third dielectric layers in the MEMS region.
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8.发明申请MEMS STRUCTURE WITH AN ETCH STOP LAYER BURIED WITHIN INTER-DIELECTRIC LAYER 审中-公开具有在电介质层内覆盖的蚀刻停止层的MEMS结构公开(公告)号：US20170036905A1
公开(公告)日：2017-02-09
申请号：US15295997
申请日：2016-10-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Li-Che Chen , Te-Yuan Wu , Chia-Huei Lin , Hui-Min Wu , Kun-Che Hsieh , Kuan-Yu Wang , Chung-Yi Chiu
CPC classification number: B81B3/0075 , B81B2207/07 , B81C1/00246 , B81C1/00801 , B81C2201/014 , B81C2203/0714 , B81C2203/0735
Abstract: A MEMS structure includes a substrate, an inter-dielectric layer on a front side of the substrate, a MEMS component on the inter-dielectric layer, and a chamber disposed within the inter-dielectric layer and through the substrate. The chamber has an opening at a backside of the substrate. An etch stop layer is disposed within the inter-dielectric layer. The chamber has a ceiling opposite to the opening and a sidewall joining the ceiling. The sidewall includes a portion of the etch stop layer.
Abstract translation: MEMS结构包括衬底，在衬底的前侧上的介电层，介电层之间的MEMS组件，以及设置在介质间介质层内并通过衬底的室。 该腔室在衬底的背面具有开口。 蚀刻停止层设置在介电层内。 该室具有与开口相对的天花板和连接天花板的侧壁。 侧壁包括蚀刻停止层的一部分。
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公开(公告)号：US10927000B2
公开(公告)日：2021-02-23
申请号：US15295997
申请日：2016-10-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Li-Che Chen , Te-Yuan Wu , Chia-Huei Lin , Hui-Min Wu , Kun-Che Hsieh , Kuan-Yu Wang , Chung-Yi Chiu
Abstract: A MEMS structure includes a substrate, an inter-dielectric layer on a front side of the substrate, a MEMS component on the inter-dielectric layer, and a chamber disposed within the inter-dielectric layer and through the substrate. The chamber has an opening at a backside of the substrate. An etch stop layer is disposed within the inter-dielectric layer. The chamber has a ceiling opposite to the opening and a sidewall joining the ceiling. The sidewall includes a portion of the etch stop layer.
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公开(公告)号：US08936960B1
公开(公告)日：2015-01-20
申请号：US13933135
申请日：2013-07-02
Applicant: United Microelectronics Corp.
Inventor： Kuan-Yu Wang , Hui-Min Wu , Kun-Che Hsieh
IPC: H01L21/00 , H01L21/4763 , H01L21/44 , B81C1/00
CPC classification number: B81B3/0072 , B81B2201/0235 , B81B2201/0242 , B81C2203/0742
Abstract: A method for fabricating an integrated device includes the following steps. First, a multi-layered structure is formed on a substrate, wherein the multi-layered structure is embedded in a lower isolation layer. Then, a bottom conductive pattern and a top conductive pattern are formed on a top surface of the lower isolation layer, wherein the top conductive pattern is on a top surface of the bottom conductive pattern. Afterwards, portions of the top conductive pattern are removed to expose portions of the bottom conductive pattern. Subsequently, an upper isolation layer is deposited on the lower isolation layer so that the upper isolation layer can be in direct contact with the portions of the bottom conductive pattern. Finally, portions of the lower isolation layer and the upper isolation layer are removed so as to expose portions of the substrate.
Abstract translation: 一种用于制造集成装置的方法包括以下步骤。 首先，在基板上形成多层结构，其中多层结构被嵌入在下隔离层中。 然后，在下隔离层的顶表面上形成底部导电图案和顶部导电图案，其中顶部导电图案位于底部导电图案的顶表面上。 之后，顶部导电图案的部分被去除以暴露底部导电图案的部分。 随后，上隔离层沉积在下隔离层上，使得上隔离层可以与底导电图案的部分直接接触。 最后，去除下隔离层和上隔离层的部分以露出基板的部分。
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