公开(公告)号：US20230307524A1

公开(公告)日：2023-09-28

申请号：US17723438

申请日：2022-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Han Wu ,  Kai-Kuen Chang ,  Ping-Hung Chiang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/66674 ,  H01L29/7801

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.

公开(公告)号：US20180097104A1

公开(公告)日：2018-04-05

申请号：US15820467

申请日：2017-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu ,  Ching-Chung Yang ,  Kai-Kuen Chang ,  Ping-Hung Chiang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7823 ,  H01L21/033 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66681

Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.

公开(公告)号：US20170077250A1

公开(公告)日：2017-03-16

申请号：US14922209

申请日：2015-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kai-Kuen Chang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4232 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor transistor device and a manufacturing method thereof. First, a semiconductor substrate is provided and a dielectric layer and a conductive layer sequentially stacked on the semiconductor substrate. Then, the conductive layer is patterned to form a gate and a dummy gate disposed at a first side of the gate and followed by forming a first spacer between the gate and the dummy gate and a second spacer at a second side of the gate opposite to the first side, wherein the first spacer includes an indentation. Subsequently, the dummy gate is removed.

Abstract translation: 本发明提供一种高压金属氧化物半导体晶体管器件及其制造方法。 首先，提供半导体衬底，并且依次层叠在半导体衬底上的电介质层和导电层。 然后，对导电层进行构图以形成设置在栅极第一侧的栅极和伪栅极，然后在栅极和伪栅极之间形成第一间隔物，并在门的第二侧形成第二间隔物， 第一侧，其中第一间隔件包括凹陷。 随后，去除虚拟门。

公开(公告)号：US20160336410A1

公开(公告)日：2016-11-17

申请号：US14739702

申请日：2015-06-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kai-Kuen Chang ,  Kun-Huang Yu

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/404 ,  H01L21/762 ,  H01L23/485 ,  H01L23/522 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a source region, a drain region, a gate, and a dummy contact. The source region and the drain region are formed in the substrate. The gate is formed on the substrate and between the source region and the drain region. The dummy contact includes a plurality of dummy plugs formed on the substrate, wherein the dummy plugs have depths decreasing towards the drain region.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括衬底，源极区，漏极区，栅极和虚拟接触。 源极区域和漏极区域形成在衬底中。 栅极形成在衬底上并且在源极区域和漏极区域之间。 虚拟触点包括形成在基板上的多个虚拟插头，其中虚拟插头具有朝向漏极区域减小的深度。

公开(公告)号：US20240154027A1

公开(公告)日：2024-05-09

申请号：US18413045

申请日：2024-01-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Han Wu ,  Kai-Kuen Chang ,  Ping-Hung Chiang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/66674 ,  H01L29/7801

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.

公开(公告)号：US11923435B2

公开(公告)日：2024-03-05

申请号：US17723438

申请日：2022-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Han Wu ,  Kai-Kuen Chang ,  Ping-Hung Chiang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/66674 ,  H01L29/7801

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.

公开(公告)号：US09722072B2

公开(公告)日：2017-08-01

申请号：US15173728

申请日：2016-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuen Chang ,  Chia-Min Hung ,  Shih-Yin Hsiao

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835

Abstract: A manufacturing method of a high-voltage metal-oxide-semiconductor (HV MOS) transistor device is provided. The manufacturing method includes the following steps. A semiconductor substrate is provided. A patterned conductive structure is formed on the semiconductor substrate. The patterned conductive structure includes a gate structure and a first sub-gate structure. The semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure. The first sub-gate structure is disposed on the first region of the semiconductor substrate. The first sub-gate structure is separated from the gate structure. A drain region is formed in the first region of the semiconductor substrate. A first contact structure is formed on the drain region and the first sub-gate structure. The drain region is electrically connected to the first sub-gate structure via the first contact structure.

公开(公告)号：US20170200650A1

公开(公告)日：2017-07-13

申请号：US14993623

申请日：2016-01-12

Applicant: United Microelectronics Corp.

Inventor： Kai-Kuen Chang ,  Shih-Yin Hsiao

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L21/823462 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/7836

Abstract: A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer.

公开(公告)号：US20170025531A1

公开(公告)日：2017-01-26

申请号：US15173728

申请日：2016-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuen Chang ,  Chia-Min Hung ,  Shih-Yin Hsiao

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835

Abstract: A manufacturing method of a high-voltage metal-oxide-semiconductor (HV MOS) transistor device is provided. The manufacturing method includes the following steps. A semiconductor substrate is provided. A patterned conductive structure is formed on the semiconductor substrate. The patterned conductive structure includes a gate structure and a first sub-gate structure. The semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure. The first sub-gate structure is disposed on the first region of the semiconductor substrate. The first sub-gate structure is separated from the gate structure. A drain region is formed in the first region of the semiconductor substrate. A first contact structure is formed on the drain region and the first sub-gate structure. The drain region is electrically connected to the first sub-gate structure via the first contact structure.

Abstract translation: 提供了高压金属氧化物半导体（HV MOS）晶体管器件的制造方法。 该制造方法包括以下步骤。 提供半导体衬底。 在半导体衬底上形成有图案的导电结构。 图案化导电结构包括栅极结构和第一子栅极结构。 半导体衬底具有分别设置在栅极结构的两个相对侧上的第一区域和第二区域。 第一子栅极结构设置在半导体衬底的第一区域上。 第一子栅极结构与栅极结构分离。 漏极区域形成在半导体衬底的第一区域中。 在漏极区域和第一子栅极结构上形成第一接触结构。 漏极区域经由第一接触结构电连接到第一子栅极结构。

公开(公告)号：US10586735B2

公开(公告)日：2020-03-10

申请号：US15886717

申请日：2018-02-01

Applicant: United Microelectronics Corp.

Inventor： Kai-Kuen Chang ,  Shih-Yin Hsiao

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/08 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8234

Abstract: A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer.