公开(公告)号：US11282799B2

公开(公告)日：2022-03-22

申请号：US16741756

申请日：2020-01-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Lin Wang ,  Ping-Chia Shih ,  Ming-Che Tsai ,  Kuei-Ya Chuang ,  Yi-Chun Teng ,  Po-Hsien Chen ,  Wan-Chun Liao

IPC: H01L23/00 ,  H01L27/088 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522

Abstract: A device for generating a security key includes a substrate, semiconductor units, contact structures, and defects. The semiconductor units are disposed on the substrate. The contact structures are disposed on and connected with the semiconductor units. The defects are disposed in at least a part of the contact structures randomly. A manufacturing method of a device for generating a security key includes the following steps. First semiconductor units are formed on a substrate. First contact structures are formed on the first semiconductor units. The first contact structures are connected with the first semiconductor units, and defects are formed in at least a part of the first contact structures randomly.

公开(公告)号：US20190013324A1

公开(公告)日：2019-01-10

申请号：US15641560

申请日：2017-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ping-Chia Shih ,  Chun-Yao Wang ,  Ming-Hua Tsai ,  Wan-Chun Liao

IPC: H01L27/11573 ,  H01L27/11568 ,  H01L21/266 ,  H01L21/28

Abstract: A method for fabricating a semiconductor integrated circuit (IC) having a SONOS memory device and a logic/analog device requiring different gate oxide layers comprises steps as follows: A substrate having a high voltage region, a memory region and a logic/analog is firstly provided. Next, a first gate oxide layer is formed on the high voltage region, the memory region and the logic/analog. The first gate oxide layer is then patterned to expose the logic/analog region and to define a first channel area and a second channel area respectively on the memory region and the high voltage region. Subsequently, a silicon oxide-silicon nitride-silicon oxide (ONO) structure is formed on the first channel area. A second gate oxide layer is then formed on the logic/analog and patterned to define a third channel area.

公开(公告)号：US11758720B2

公开(公告)日：2023-09-12

申请号：US18077183

申请日：2022-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Min Hung ,  Ping-Chia Shih ,  Che-Hao Kuo ,  Kuei-Ya Chuang ,  Ssu-Yin Liu ,  Po-Hsien Chen ,  Wan-Chun Liao

IPC: H10B41/30 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

公开(公告)号：US11552088B2

公开(公告)日：2023-01-10

申请号：US17198268

申请日：2021-03-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Min Hung ,  Ping-Chia Shih ,  Che-Hao Kuo ,  Kuei-Ya Chuang ,  Ssu-Yin Liu ,  Po-Hsien Chen ,  Wan-Chun Liao

IPC: H01L27/11521 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

公开(公告)号：US20210217708A1

公开(公告)日：2021-07-15

申请号：US16741756

申请日：2020-01-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Lin Wang ,  Ping-Chia Shih ,  Ming-Che Tsai ,  Kuei-Ya Chuang ,  Yi-Chun Teng ,  Po-Hsien Chen ,  Wan-Chun Liao

IPC: H01L23/00 ,  H01L27/088 ,  H01L23/522 ,  H01L21/8234 ,  H01L21/768

Abstract: A device for generating a security key includes a substrate, semiconductor units, contact structures, and defects. The semiconductor units are disposed on the substrate. The contact structures are disposed on and connected with the semiconductor units. The defects are disposed in at least a part of the contact structures randomly. A manufacturing method of a device for generating a security key includes the following steps. First semiconductor units are formed on a substrate. First contact structures are formed on the first semiconductor units. The first contact structures are connected with the first semiconductor units, and defects are formed in at least a part of the first contact structures randomly.

公开(公告)号：US20240006345A1

公开(公告)日：2024-01-04

申请号：US17874299

申请日：2022-07-27

Applicant: United Microelectronics Corp.

Inventor： Po Hsien Chen ,  Ping-Chia Shih ,  Che Hao Kuo ,  Chia-Min Hung ,  Ching-Hua Yeh ,  Wan-Chun Liao

IPC: H01L23/00 ,  H04L9/32 ,  H01L29/06

CPC classification number: H01L23/57 ,  H04L9/3278 ,  H01L29/0649

Abstract: A physical unclonable function (PUF) generator including a substrate and semiconductor units is provided. Each of the semiconductor units includes an isolation structure, a first conductive line, and a second conductive line. The isolation structure is located in the substrate. The isolation structure has a first protrusion portion and a recess. The first protrusion portion and the recess are adjacent to each other. The first conductive line is located above the first protrusion portion and the recess. The second conductive line is located above the first conductive line. At least one short circuit randomly exists between at least one of the first conductive lines and at least one of the second conductive lines in at least one of the semiconductor units.

公开(公告)号：US11616069B2

公开(公告)日：2023-03-28

申请号：US17073443

申请日：2020-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ping-Chia Shih ,  Kuei-Ya Chuang ,  Chuang-Hsin Chueh ,  Ming-Che Tsai ,  Wen-Lin Wang ,  Yi-Chun Teng ,  Ssu-Yin Liu ,  Wan-Chun Liao

IPC: H01L27/11521

Abstract: The present application discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a gate dielectric layer, a floating gate, a first dielectric layer and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer and has at least one tip on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed above the first dielectric layer and at least partially overlaps the floating gate.

公开(公告)号：US20220293615A1

公开(公告)日：2022-09-15

申请号：US17198268

申请日：2021-03-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Min Hung ,  Ping-Chia Shih ,  Che-Hao Kuo ,  Kuei-Ya Chuang ,  Ssu-Yin Liu ,  Po-Hsien Chen ,  Wan-Chun Liao

IPC: H01L27/11521 ,  H01L29/423 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

公开(公告)号：US10177165B1

公开(公告)日：2019-01-08

申请号：US15641560

申请日：2017-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ping-Chia Shih ,  Chun-Yao Wang ,  Ming-Hua Tsai ,  Wan-Chun Liao

IPC: H01L27/11573 ,  H01L27/11568 ,  H01L21/266 ,  H01L21/28 ,  H01L29/51

Abstract: A method for fabricating a semiconductor integrated circuit (IC) having a SONOS memory device and a logic/analog device requiring different gate oxide layers comprises steps as follows: A substrate having a high voltage region, a memory region and a logic/analog is firstly provided. Next, a first gate oxide layer is formed on the high voltage region, the memory region and the logic/analog. The first gate oxide layer is then patterned to expose the logic/analog region and to define a first channel area and a second channel area respectively on the memory region and the high voltage region. Subsequently, a silicon oxide-silicon nitride-silicon oxide (ONO) structure is formed on the first channel area. A second gate oxide layer is then formed on the logic/analog and patterned to define a third channel area.