公开(公告)号：US12248706B2

公开(公告)日：2025-03-11

申请号：US18220933

申请日：2023-07-12

Applicant: Western Digital Technologies, Inc.

Inventor： Rotem Sela ,  Meytal Soffer ,  Asher Druck

IPC: G06F12/00 ,  G06F3/06

Abstract: A data storage device has a cache and a non-volatile memory. Instead of flushing the entire cache to the non-volatile memory in response to a command from a host, the data storage device flushes only the cached data that is associated with an identifier provided by the host. This allows the cached data associated with the identifier to be flushed more quickly. The data storage device can also prioritize queued commands that are associated with the identifier.

公开(公告)号：US12124377B2

公开(公告)日：2024-10-22

申请号：US18222034

申请日：2023-07-14

Applicant: Western Digital Technologies, Inc.

Inventor： Rotem Sela ,  Hadas Oshinsky ,  Einav Zilberstein

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F12/0873 ,  G06F12/123

CPC classification number: G06F12/0873 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0679 ,  G06F12/0253 ,  G06F12/123

Abstract: Zoned memory typically requires write commands to be sent from a host to a data storage device in logical block address (LBA) sequential order. Instead of rejecting out-of-order write commands, the data storage device can execute those commands and internally deal with the out-of-order problem. For example, the data storage device can use a special zone logical-to-physical address table, use a temporary zone data buffer, and/or store a data's LBA in a header for later matching.

公开(公告)号：US20240332110A1

公开(公告)日：2024-10-03

申请号：US18361147

申请日：2023-07-28

Applicant: Western Digital Technologies, Inc.

Inventor： Rotem Sela ,  Mahmud Asfur ,  Boaz Greenberg

IPC: H01L23/32 ,  H01L23/00 ,  H01L23/40 ,  H01L23/498 ,  H01L25/18 ,  H01R13/502 ,  H01R33/88 ,  H10B80/00

CPC classification number: H01L23/32 ,  H01L23/40 ,  H01L23/49833 ,  H01L24/72 ,  H01L25/18 ,  H01R13/502 ,  H01R33/88 ,  H10B80/00 ,  H01L23/49811 ,  H01L24/32 ,  H01L2224/32225 ,  H01L2224/72

Abstract: A multi-chip package includes a substrate, a first semiconductor module mounted on the substrate, an interposer mounted on the first semiconductor module and a second semiconductor module detachably coupled to the interposer. A housing at least partially encloses the first and second semiconductor modules and the interposer. The housing is configured to transition between a closed configuration and an open configuration. In the closed configuration, the second semiconductor module is fixed in position relative to the interposer and electrically connected to the substrate via the interposer, and in the open configuration the second semiconductor module is detachable from the interposer. The second semiconductor module being detachable from the interposer allows for the second semiconductor module to be selectively replaced to improve the longevity of the multi-chip package.

公开(公告)号：US11169744B2

公开(公告)日：2021-11-09

申请号：US16836679

申请日：2020-03-31

Applicant: Western Digital Technologies, Inc.

Inventor： David C. Brief ,  Rotem Sela ,  Opher Lieber

IPC: G06F11/20 ,  G06F3/06 ,  G06F12/1009

Abstract: Data may be read from a data storage device using host performance booster (HPB). An encoded HPB entry in a read command provides the PBA (Physical Block Address) as well as the run length. The LBA (Logical Block Address), PBA, and run length are placed in an HPB read buffer table. The HPB read buffer table is located in the host device. When the read command is received by the data storage device, the data storage device reads the LBA, transfer length, and HPB entry from the read command. The HPB entry contains the PBA for the LBA as well as the run length for the data to be read. For non-sequential reads, the HPB contains the LBA, transfer length, and reference to a write buffer table that is stored in the data storage device.

公开(公告)号：US11137914B2

公开(公告)日：2021-10-05

申请号：US16405818

申请日：2019-05-07

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Rotem Sela ,  Yiftach Tzori

IPC: G06F3/06 ,  G11C11/409 ,  G06F9/38

Abstract: A hybrid command is proposed for interacting with a non-volatile memory device. The hybrid command enables a host connected to the non-volatile memory device to both send and receive data using a single command, which removes the need to use separate commands for sending and receiving. Using the one command rather than separate commands increases system performance.

公开(公告)号：US20210165595A1

公开(公告)日：2021-06-03

申请号：US16700501

申请日：2019-12-02

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Rotem Sela ,  Yoseph Pinto

IPC: G06F3/06 ,  G11C13/00

Abstract: Technology for detecting a capability set of a removable integrated circuit card, such as a removable memory card, is disclosed. The removable integrated circuit card has one or more capability pads that indicate a capability set of the removable integrated circuit card. The physical condition may be a physical configuration of one or more capability pads, such as size or location of a capability pad. A host device is able to determine the capability set of the removable integrated circuit card based on the physical condition of the capability pads. The host device may determine the capability set without the card being powered on, without reading a register in the card, or without exchanging commands with the card.

公开(公告)号：US10438664B2

公开(公告)日：2019-10-08

申请号：US15435668

申请日：2017-02-17

Applicant: Western Digital Technologies, Inc.

Inventor： Rotem Sela ,  Miki Sapir ,  Enosh Levi

IPC: G11C16/10 ,  G11C16/22 ,  G06F21/31 ,  G06F21/57 ,  G11C7/24

Abstract: A non-volatile memory device uses physical authentication to enable the secure programming of a boot partition, when the boot partition is write protected. This physical authentication can also be used to enable other features/functions.

公开(公告)号：US10372341B2

公开(公告)日：2019-08-06

申请号：US15636496

申请日：2017-06-28

Applicant: Western Digital Technologies, Inc.

Inventor： Hadas Oshinsky ,  Rotem Sela ,  Amir Shaharabany

IPC: G06F3/06 ,  G06F12/02

Abstract: A controller addresses portions of non-volatile memory via a memory interface using physical addresses and addresses portions of host data via the host interface using logical addresses. The controller maintains logical to physical mappings and physical to logical mappings for the logical addresses and the physical addresses. The controller is configured to move data from a source logical address to a destination logical address by updating logical to physical mappings and physical address to logical mappings without instructing the non-volatile memory to move the data between physical locations. In one embodiment, this process is used to implement a command to move or defragment data.

公开(公告)号：US20180322051A1

公开(公告)日：2018-11-08

申请号：US15611510

申请日：2017-06-01

Applicant: Western Digital Technologies, Inc.

Inventor： Tal Heller ,  Hadas Oshinsky ,  Rotem Sela ,  Einav Zilberstein ,  Amir Shaharabany ,  Yigal Eli

IPC: G06F12/0804 ,  G06F12/0806 ,  G06F12/0868

CPC classification number: G06F12/0804 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G11C7/20

Abstract: A storage system and method are provided for flush optimization. In one embodiment, a storage system is provided comprising a cache, a non-volatile memory, and a controller. The controller is configured to: store, in the cache, data received from a host and to be written in the non-volatile memory; receive a command from the host to move the data stored in the cache into the non-volatile memory; without having executed the command, send a confirmation to the host that the command was executed; and execute the command after sending the continuation to the host.

公开(公告)号：US20240378151A1

公开(公告)日：2024-11-14

申请号：US18359028

申请日：2023-07-26

Applicant: Western Digital Technologies, Inc.

Inventor： Rotem Sela ,  Amir Segev

IPC: G06F12/0855 ,  G06F12/10

Abstract: A data storage device implements a Zoned Namespace (ZNS) storage architecture. The data storage device delays the execution of write commands that are received out of sequence instead of rejecting the write commands. The write commands that are received out of sequence are reordered according to a logical block address (LBA) associated with each write command. The data storage device also checks for deadlock conditions that may arise due to the execution of the write commands being delayed and/or due to the write commands being reordered.