公开(公告)号：US06596639B1

公开(公告)日：2003-07-22

申请号：US09415529

申请日：1999-10-08

申请人： William G. Easter ,  Sudhanshu Misra ,  Vivek Saxena

发明人： William G. Easter ,  Sudhanshu Misra ,  Vivek Saxena

IPC分类号： H01L21302

CPC分类号： H01L21/31053

摘要： The present invention provides a method of manufacturing an integrated circuit including planarizing a semiconductor wafer surface. In one embodiment, the method comprises forming a dielectric layer over a first level having an irregular topography, depositing a sacrificial material over the dielectric layer, and then planarizing the semiconductor wafer surface to a planar surface. More specifically, the dielectric layer forms such that it substantially conforms to the irregular topography of the first level. The sacrificial material is formed to a substantially planar surface over the dielectric layer. Thus, the sacrificial material provides a substantially uniform chemical/mechanical planarization (CMP) process removal rate across the semiconductor wafer surface. In the ensuing step, planarizing the semiconductor wafer surface to a planar surface removes the sacrificial material and a portion of the dielectric layer with a CMP process.

摘要翻译： 本发明提供一种制造集成电路的方法，该集成电路包括使半导体晶片表面平坦化。 在一个实施例中，该方法包括在具有不规则形貌的第一层上形成电介质层，在电介质层上沉积牺牲材料，然后将半导体晶片表面平坦化为平坦表面。 更具体地，电介质层形成为使得其基本上符合第一级的不规则形貌。 牺牲材料形成在电介质层上的基本平坦的表面上。 因此，牺牲材料在半导体晶片表面上提供基本均匀的化学/机械平面化（CMP）工艺去除速率。 在随后的步骤中，将半导体晶片表面平面化成平面以CMP工艺去除牺牲材料和介电层的一部分。

公开(公告)号：US06436807B1

公开(公告)日：2002-08-20

申请号：US09484310

申请日：2000-01-18

申请人： Donald Thomas Cwynar ,  Sudhanshu Misra ,  Dennis Okumu Ouma ,  Vivek Saxena ,  John Michael Sharpe

发明人： Donald Thomas Cwynar ,  Sudhanshu Misra ,  Dennis Okumu Ouma ,  Vivek Saxena ,  John Michael Sharpe

IPC分类号： H01L214763

CPC分类号： H01L23/528 ,  H01L21/76819 ,  H01L2924/0002 ,  Y10S438/926 ,  H01L2924/00

摘要： A method for making a layout for an interconnect layer of a semiconductor device to facilitate uniformity of planarization during manufacture of the semiconductor device includes determining an active interconnect feature density for each of a plurality of layout regions of the interconnect layout. The method further includes adding dummy fill features to each layout region to obtain a desire density of active interconnect features and dummy fill features to facilitate uniformity of planarization during manufacturing of the semiconductor device. By adding dummy fill features to obtain a desired density of active interconnect features and dummy fill features, dummy fill features are not unnecessarily added, and each layout region has a uniform density.

摘要翻译： 制造用于半导体器件的互连层的布局的方法，以便在半导体器件的制造期间促进平坦化的均匀性包括确定互连布局的多个布局区域中的每一个的有源互连特征密度。 该方法还包括向每个布局区域添加虚拟填充特征以获得有源互连特征和虚拟填充特征的期望密度，以便于在半导体器件的制造期间平坦化的均匀性。 通过添加虚拟填充特征以获得所需的有源互连特征和虚拟填充特征的密度，虚拟填充特征不会被不必要地添加，并且每个布局区域具有均匀的密度。

公开(公告)号：US06683382B2

公开(公告)日：2004-01-27

申请号：US10147384

申请日：2002-05-16

申请人： Donald Thomas Cwynar ,  Sudhanshu Misra ,  Dennis Okumu Ouma ,  Vivek Saxena ,  John Michael Sharpe

发明人： Donald Thomas Cwynar ,  Sudhanshu Misra ,  Dennis Okumu Ouma ,  Vivek Saxena ,  John Michael Sharpe

IPC分类号： H01L2710

CPC分类号： H01L23/528 ,  H01L21/76819 ,  H01L2924/0002 ,  Y10S438/926 ,  H01L2924/00

摘要： A semiconductor device with an interconnect layer having a plurality of layout regions of active interconnects and dummy fills for uniform planarization. In one embodiment, the device will have at least one interconnect layer with a plurality of layout regions overlying the semiconductor substrate. Each layout region will comprise an active interconnect feature region and a dummy fill feature region adjacent thereto for facilitating uniformity of planarization during manufacturing. Each dummy fill region in each layout region will have a different density with respect to other dummy fill regions in other layout regions, so that the combined density of the active interconnect feature region and the dummy fill feature region in a layout region will be substantially uniform with respect to a similar combined density in each of the other layout regions.

摘要翻译： 具有互连层的半导体器件具有多个有源互连的布局区域和用于均匀平坦化的虚拟填充。 在一个实施例中，该器件将具有至少一个具有覆盖半导体衬底的多个布局区域的互连层。 每个布局区域将包括有源互连特征区域和与其相邻的虚拟填充特征区域，以便于制造过程中平坦化的均匀性。 每个布局区域中的每个虚拟填充区域相对于其他布局区域中的其它虚拟填充区域将具有不同的密度，使得布局区域中的有源互连特征区域和虚拟填充特征区域的组合密度将基本均匀 相对于每个其他布局区域中的类似的组合密度。

公开(公告)号：US06439972B2

公开(公告)日：2002-08-27

申请号：US09894117

申请日：2001-06-28

申请人： Sudhanshu Misra ,  Pradip Kumar Roy ,  Sundar Srinivasaan Chetlur ,  Vivek Saxena

发明人： Sudhanshu Misra ,  Pradip Kumar Roy ,  Sundar Srinivasaan Chetlur ,  Vivek Saxena

IPC分类号： B24B2118

CPC分类号： B24B37/044 ,  C09G1/02

摘要： A polishing fluid comprising a distributed organic phase and a continuous aqueous phase, each phase comprising at least one complexing agent. The aqueous phase also having abrasive particles dispersed therein. Reaction products generated during polishing interact with the aqueous phase complexing agent to form water soluble metallic complexes, the water soluble metallic complexes diffuse to an organic/water interface where they release complexing agent molecules in the aqueous phase and generate metal ions which interact with the organic phase complexing agent to form organometallic complexes. Further disclosed is a polishing method, a semiconductor device and semiconductor device fabrication method utilizing the polishing fluid.

摘要翻译： 一种包含分布有机相和连续水相的抛光液，每相包含至少一种络合剂。 水相中也分散有磨粒。 在抛光过程中产生的反应产物与水相络合剂相互作用以形成水溶性金属络合物，水溶性金属络合物扩散到有机/水界面，在那里它们释放水相中的络合剂分子并产生与有机物相互作用的金属离子 相络合剂形成有机金属络合物。 进一步公开了一种利用抛光液的抛光方法，半导体器件和半导体器件制造方法。

公开(公告)号：US06328633B1

公开(公告)日：2001-12-11

申请号：US09483785

申请日：2000-01-14

申请人： Sudhanshu Misra ,  Pradip Kumar Roy ,  Sundar Srinivasaan Chetlur ,  Vivek Saxena

发明人： Sudhanshu Misra ,  Pradip Kumar Roy ,  Sundar Srinivasaan Chetlur ,  Vivek Saxena

IPC分类号： B24B100

CPC分类号： B24B37/044 ,  C09G1/02

摘要： A polishing fluid comprising a distributed organic phase and a continuous aqueous phase, each phase comprising at least one complexing agent. The aqueous phase also having abrasive particles dispersed therein. Reaction products generated during polishing interact with the aqueous phase complexing agent to form water soluble metallic complexes, the water soluble metallic complexes diffuse to an organic/water interface where they release complexing agent molecules in the aqueous phase and generate metal ions which interact with the organic phase complexing agent to form organometallic complexes. Further disclosed is a polishing method, a semiconductor device and semiconductor device fabrication method utilizing the polishing fluid.

公开(公告)号：US20050246756A1

公开(公告)日：2005-11-03

申请号：US10833430

申请日：2004-04-28

申请人： John Leddy ,  Vivek Saxena

发明人： John Leddy ,  Vivek Saxena

IPC分类号： H04N7/173 ,  H04N7/22

CPC分类号： H04N7/22

摘要： Various channels containing digital data for CATV services are distributed over the HFC CATV network from the headend. Digital data is modulated on RF sub-carriers within an allocated downstream RF spectrum. The allocated downstream RF spectrum is split such that different parts of the RF spectrum are transmitted by WDM lasers in a transmitter system including an array of such lasers. The transmitter system utilizes WDM to combine different wavelengths from the laser array on the transmitter side and then launches them onto a single fiber. The transmitted optical signals impinge on a single photo device which reproduces the combined RF spectrum at its output.

摘要翻译： 包含CATV服务数字数据的各种频道从头端分配在HFC CATV网络上。 在分配的下行RF频谱内的RF子载波上调制数字数据。 分配的下行RF频谱被分割，使得RF频谱的不同部分由包括这种激光器的阵列的发射机系统中的WDM激光器发射。 发射机系统利用WDM将来自发射机侧的激光阵列的不同波长组合起来，然后将其发射到单个光纤上。 所传输的光信号照射在其输出端再现组合RF频谱的单个照相装置上。

公开(公告)号：US06576522B2

公开(公告)日：2003-06-10

申请号：US09733570

申请日：2000-12-08

申请人： Sundar Srinivasan Chetlur ,  Pradip Kumar Roy ,  Minesh Amrat Patel ,  Sidhartha Sen ,  Vivek Saxena

发明人： Sundar Srinivasan Chetlur ,  Pradip Kumar Roy ,  Minesh Amrat Patel ,  Sidhartha Sen ,  Vivek Saxena

IPC分类号： H01L21336

CPC分类号： H01L21/324 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3003 ,  H01L21/76828 ,  H01L21/76834

摘要： A method for deuterium sintering to improve the hot carrier aging of an integrated circuit includes (a) providing a partially fabricated integrated circuit structure comprising a semiconductor substrate and a dielectric layer formed on at least a portion of the substrate, the dielectric layer having at least one conductive material via plug formed therein and (b) sintering the structure in the presence of a gas comprising deuterium-containing components at high temperatures prior to a metallization layer being deposited on the structure.

公开(公告)号：US20200007039A1

公开(公告)日：2020-01-02

申请号：US16021712

申请日：2018-06-28

申请人： Amit Jain ,  Sameer Shekhar ,  Alexander Lyakhov ,  Jonathan Douglas ,  Vivek Saxena

发明人： Amit Jain ,  Sameer Shekhar ,  Alexander Lyakhov ,  Jonathan Douglas ,  Vivek Saxena

IPC分类号： H02M3/158

摘要： Techniques and mechanisms for mitigating an overshoot of a supply voltage provided with a voltage regulator (VR). In an embodiment, buck converter functionality of a VR is provided with first circuitry comprising a first inductor and first switch circuits variously coupled thereto. Second circuitry of the VR comprises a second inductor and second switch circuits variously coupled thereto. In response to an indication of a voltage overshoot condition, respective states of the first switch circuits and the second switch circuits are configured to enable a conductive path for dissipating energy with the first inductor, the second inductor, and various ones of the first switch circuits and the second switch circuits. In another embodiment, mitigating the voltage overshoot condition comprises alternately toggling between two different configurations of the second switch circuits.

公开(公告)号：US07496860B2

公开(公告)日：2009-02-24

申请号：US10881343

申请日：2004-06-30

申请人： Vivek Saxena ,  Sriram Srinivasan ,  Joseph Adams

发明人： Vivek Saxena ,  Sriram Srinivasan ,  Joseph Adams

IPC分类号： G06F3/048 ,  G06F17/50

CPC分类号： G06Q10/10 ,  G06Q10/0633

摘要： A method and system for managing complex projects uses a framework having workflow maps containing activity blocks that provide detailed, easily accessible information within the framework about the project. The framework links functional groups, their associated activities, and the dependences between activities. The detailed, prescriptive instructions provided at each stage in the process creates in-process quality control, reducing the likelihood of costly mistakes and turnbacks. Implementing the framework as a web-based application allows easy access to the framework as well as data entered into the framework for future analysis, making it easy to identify improvement opportunities in the framework.

摘要翻译： 用于管理复杂项目的方法和系统使用框架，该框架具有包含活动块的工作流映射，在框架内提供关于项目的详细，易于访问的信息。 框架链接功能组，其相关活动以及活动之间的依赖关系。 该过程每个阶段提供的详细说明性说明都会创建过程中的质量控制，从而降低代价高昂的错误和折返的可能性。 将框架作为基于Web的应用程序实现，可以轻松访问框架以及输入到框架中的数据，以便将来进行分析，从而可以轻松地识别框架中的改进机会。

公开(公告)号：US20060005157A1

公开(公告)日：2006-01-05

申请号：US10881343

申请日：2004-06-30

申请人： Vivek Saxena ,  Sriram Srinivasan ,  Joseph Adams

发明人： Vivek Saxena ,  Sriram Srinivasan ,  Joseph Adams

IPC分类号： G06F9/44 ,  G06F17/60

CPC分类号： G06Q10/10 ,  G06Q10/0633

摘要： A method and system for managing complex projects uses a framework having workflow maps containing activity blocks that provide detailed, easily accessible information within the framework about the project. The framework links functional groups, their associated activities, and the dependences between activities. The detailed, prescriptive instructions provided at each stage in the process creates in-process quality control, reducing the likelihood of costly mistakes and turnbacks. Implementing the framework as a web-based application allows easy access to the framework as well as data entered into the framework for future analysis, making it easy to identify improvement opportunities in the framework.