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公开(公告)号：US09508745B1
公开(公告)日：2016-11-29
申请号：US14994633
申请日：2016-01-13
Inventor： Yuanfu Liu
CPC classification number: H01L27/1222 , H01L27/127 , H01L27/323 , H01L27/3272 , H01L29/66765 , H01L29/78621 , H01L29/78633 , H01L29/78648 , H01L29/78678 , H01L29/78696 , H01L51/0023 , H01L51/102
Abstract: An array substrate and a fabricating method thereof are disclosed. The array substrate has a transparent substrate, a buffer layer, a first/second gate pattern, a transparent insulating layer and a first/second polysilicon pattern. The buffer layer is located on first/second portions of the transparent substrate. The first/second gate patterns are formed on the buffer layer and located respectively on the first/second portions. The transparent insulating layer covers the first/second gate patterns and the buffer layer. The first/second polysilicon patterns are formed on the transparent insulating layer, and have neighboring first/second regions and neighboring third/fourth regions; the second/fourth regions are first/second lightly doped polysilicon regions respectively; the first region and the first gate pattern have an identical first patterning shape; and the third region and the second gate pattern have an identical second patterning shape. The array substrate has a simple process, low producing cost, and high product yield.
Abstract translation: 公开了阵列基板及其制造方法。 阵列基板具有透明基板，缓冲层，第一/第二栅极图案，透明绝缘层和第一/第二多晶硅图案。 缓冲层位于透明基板的第一/第二部分上。 第一/第二栅极图案形成在缓冲层上并分别位于第一/第二部分上。 透明绝缘层覆盖第一/第二栅极图案和缓冲层。 第一/第二多晶硅图案形成在透明绝缘层上，并且具有相邻的第一/第二区域和相邻的第三/第四区域; 第二/第四区域分别是第一/第二轻掺杂多晶硅区域; 第一区域和第一栅极图案具有相同的第一图案形状; 并且第三区域和第二栅极图案具有相同的第二图案形状。 阵列基板具有工艺简单，生产成本低，产品成品率高。
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公开(公告)号：US20190187500A1
公开(公告)日：2019-06-20
申请号：US16285130
申请日：2019-02-25
Inventor： Yuanfu Liu
IPC: G02F1/1368 , H01L29/786 , H01L27/12 , H01L29/66 , H01L21/266 , H01L21/265 , G02F1/1362
CPC classification number: G02F1/1368 , G02F1/136227 , G02F2001/136231 , G02F2202/104 , H01L21/26513 , H01L21/266 , H01L27/1288 , H01L29/66757 , H01L29/66765 , H01L29/78621 , H01L29/78633
Abstract: A TFT substrate includes, stacked in sequence from bottom to top, a backing plate, a gate electrode, a gate insulation layer, an active layer and a source electrode and a drain electrode, a first passivation layer, a planarization layer, a common electrode, a second passivation layer, and a pixel electrode. The source electrode and the drain electrode are respectively located at two sides of the active layer. The active layer includes two lightly-ion-doped semiconductor layers respectively connected with the source and drain electrodes and a channel-zone semiconductor layer located therebetween. The first passivation layer and the planarization layer include a first via formed therein and corresponding to the drain electrode. The second passivation layer has a second via extending through a portion of the second passivation layer inside the first via. The pixel electrode is connected through the second via to the drain electrode.
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公开(公告)号：US11315511B2
公开(公告)日：2022-04-26
申请号：US16061556
申请日：2018-03-08
Inventor： Yuanfu Liu
IPC: G09G3/36 , G02F1/1333 , G02F1/1343 , G02F1/1362
Abstract: A common electrode of a display panel is disclosed. The common electrode is located at a side of a gate driving device of the display panel, and the common electrode includes multiple main trunk electrodes arranged sequentially along a row direction, along the row direction, from a side closed to the gate driving device to a side away from the gate driving electrode, in adjacent two main trunk electrodes, a common voltage on a previous main trunk electrode is less than or equal to a common voltage on a next main trunk electrode, and a common voltage of a first main trunk electrode is less than a common voltage on a last main trunk electrode. The present invention can reduce the uneven display caused by RC delay on the transmission of the scanning signal.
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公开(公告)号：US10658403B2
公开(公告)日：2020-05-19
申请号：US15995149
申请日：2018-06-01
Inventor： Yuanfu Liu
IPC: H01L27/12 , H01L29/786 , H01L29/423 , H01L29/66
Abstract: A manufacturing method of a TFT substrate uses a top gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield can be increased to effectively improve productivity. Heavy and light ion doping can be simultaneously achieved with one single doping operation so that manufacturing cost can be reduced. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to contact the two ends of the active layer thereby effectively reducing contact resistance and improving product yield. Also provided is a TFT substrate manufactured with the method.
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公开(公告)号：US10345659B2
公开(公告)日：2019-07-09
申请号：US15916435
申请日：2018-03-09
Inventor： Yuanfu Liu
IPC: G02F1/1362
Abstract: The present disclosure provides an array substrate, the array substrate includes a plurality of array blocks arranged at intervals, wherein each array block includes a plurality of sub-array substrates arranged at intervals, at least one of a periphery of the array substrate, a periphery of the array block, and a periphery of the display area of the sub-array substrate is arranged with an electrostatic protection structure, the electrostatic protection structure is a transparent metal oxide wire, or a metal wire and a transparent conductive metal oxide wire arranged in layers. The existence of the electrostatic protection structure can effectively shield the outside static electricity. The disclosure also provides a liquid crystal display panel adopting the array substrate.
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Patent Agency Ranking
公开(公告)号：US20170207251A1
公开(公告)日：2017-07-20
申请号：US15137003
申请日：2016-04-25
Inventor： Yuanfu Liu
IPC: H01L27/12 , H01L29/45 , H01L29/49 , H01L29/786
CPC classification number: H01L27/1255 , H01L27/1222 , H01L27/124 , H01L27/1248 , H01L29/456 , H01L29/4908 , H01L29/495 , H01L29/78633 , H01L29/78675
Abstract: Provided is a TFT array substrate, which increases the area of a drain electrode of a TFT within a light-shielding zone to have the drain electrode overlapping a portion of a horizontal projection of a common electrode, wherein the drain electrode and the common electrode constitute a first storage capacitor and a pixel electrode and the common electrode constitute a second storage capacitor. The pixel electrode and the drain electrode are electrically connected and thus are of the same potential. The first storage capacitor and the second storage capacitor are connected in parallel and collectively form a storage capacitor such that the storage capacitor has a capacity that is equal to the sum of capacities of the first storage capacitor and the second storage capacitor, whereby, without reducing aperture ratio, the capacity of the storage capacitor is increased, crosstalk and image sticking are alleviated, and product display quality is enhanced.
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公开(公告)号：US20170200750A1
公开(公告)日：2017-07-13
申请号：US15137001
申请日：2016-04-25
Inventor： Yuanfu Liu , Fuhsiung Tang
IPC: H01L27/12 , G02F1/1339 , G02F1/1333 , G02F1/1368 , H01L21/311 , G06F3/041
CPC classification number: H01L27/1288 , G02F1/13338 , G02F1/1339 , G02F2001/133357 , G02F2001/133388 , G02F2001/13606 , G02F2001/136236 , G02F2202/28 , G06F3/0412 , G06F3/044 , G06F2203/04103 , H01L21/31144 , H01L27/1248 , H01L27/1259
Abstract: Provided is a method for manufacturing an array substrate, in which a planarization layer mask includes a strip pattern that is provided for forming a groove and has two opposite sides along which taper modification patterns are provided so as to reduce taper of a groove formed in a planarization layer, making a slope thereof less steep, thereby preventing shorting of signal lines caused by residues of metal or ITO in a subsequent operation and thus increasing product yield. For the groove associated portion of an array substrate involving an in-cell touch structure, there is no need to change line for the touch sensing lines so as to lower down the difficulty of the operation and increase product yield.
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公开(公告)号：US10424607B2
公开(公告)日：2019-09-24
申请号：US15441245
申请日：2017-02-24
Inventor： Yuanfu Liu
IPC: H01L27/12 , H01L29/786 , H01L29/423 , H01L29/66
Abstract: A manufacturing method of a TFT substrate uses a top gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield can be increased to effectively improve productivity. Heavy and light ion doping can be simultaneously achieved with one single doping operation so that manufacturing cost can be reduced. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to contact the two ends of the active layer thereby effectively reducing contact resistance and improving product yield. Also provided is a TFT substrate manufactured with the method.
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公开(公告)号：US10365522B2
公开(公告)日：2019-07-30
申请号：US15520695
申请日：2017-03-17
Inventor： Yuanfu Liu
IPC: G02F1/1345 , H01L27/12 , H01L27/13 , G09G3/36 , G02F1/1368
Abstract: A GOA driving panel is disclosed. The GOA driving panel includes an active area and a non-active area arranged at two opposite sides of the active area. The non-active area is provided with a plurality of GOA driving units, and each GOA driving unit is connected with one corresponding scanning line in the active area for outputting a scanning signal to the scanning line. The non-active area is further provided with a plurality of signal waveform delay units, and each signal waveform delay unit is arranged between a GOA driving unit and a corresponding scanning line.
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公开(公告)号：US10331001B2
公开(公告)日：2019-06-25
申请号：US15441246
申请日：2017-02-24
Inventor： Yuanfu Liu
IPC: G02F1/1368 , G02F1/1362 , H01L29/786 , H01L29/66 , H01L21/265 , H01L21/266 , H01L27/12
Abstract: A manufacturing method of a TFT substrate uses a bottom gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield and increase productivity are effectively improved. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to get in connection with the two ends of the active layer so as to effectively reduce contact resistance and improve product yield. Also provided is a TFT substrate manufactured with the method.
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