公开(公告)号：US12019576B2

公开(公告)日：2024-06-25

申请号：US17879675

申请日：2022-08-02

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Ygal Arbel ,  Sagheer Ahmad ,  Abbas Morshed

IPC: G06F13/40

CPC classification number: G06F13/4027 ,  G06F2213/40

Abstract: Embodiments herein describe a decentralized chip-to-chip (C2C) interface architecture to transport memory mapped traffic amongst heterogeneous IC devices in a packetized, scalable, and configurable manner. An IC chip may include functional circuitry that exchanges memory-mapped traffic with an off-chip device, a NoC that packetizes and de-packetizes memory-mapped traffic and routes the packetized memory-mapped traffic between the functional circuitry and the off-chip device, and NoC inter-chip bridge (NICB) circuitry that interfaces between the NoC and the off-chip device over C2C interconnections. The NICB circuitry may be configurable in a full mode to map packetized memory-mapped traffic to the C2C interconnections in a 1:1 fashion and in a compressed to map packetized memory-mapped traffic to the C2C interconnections in a less-than 1:1 fashion.

公开(公告)号：US12019908B2

公开(公告)日：2024-06-25

申请号：US17389272

申请日：2021-07-29

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Shishir Kumar ,  Sagheer Ahmad ,  Abbas Morshed ,  Aman Gupta

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0653 ,  G06F3/0679

Abstract: Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.

公开(公告)号：US11010322B1

公开(公告)日：2021-05-18

申请号：US16448727

申请日：2019-06-21

Applicant: XILINX, INC.

Inventor： Abbas Morshed

IPC: G06F13/40 ,  G06F11/07

Abstract: A network on a chip (NOC) peripheral interface (NPI) includes an NPI root, a plurality of switches coupled to the NPI root, and a plurality of NPI protocol blocks coupled to the plurality of switches. The NPI root, the plurality of switches, and the plurality of NPI protocol blocks are configured to route signals received from a master to a plurality of circuit blocks. A non-service command is routed to an intended circuit block of the plurality of circuit blocks. A switch of the plurality of switches or an NPI protocol block of the plurality of NPI protocol blocks generate a response message for a service command query with the destination address associated with the intended circuit block that is received from the master instead of routing the service command query to the intended circuit block.

公开(公告)号：US11985061B1

公开(公告)日：2024-05-14

申请号：US17227258

申请日：2021-04-09

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Abbas Morshed ,  Aman Gupta ,  Sagheer Ahmad

IPC: H04L45/302 ,  G06F15/78 ,  H04L45/00 ,  H04L45/42 ,  H04L45/745

CPC classification number: H04L45/302 ,  G06F15/7825 ,  H04L45/42 ,  H04L45/566 ,  H04L45/745 ,  H04L45/34

Abstract: Embodiments herein describe an integrated circuit that includes a network on chip (NoC) where an egress logic block or switch performs a route lookup for a subsequent (e.g., downstream) switch in the NoC (referred to herein as look-ahead routing). After receiving the packet and a port ID from the egress logic block or the switch, the downstream switch knows, without performing route lookup of its own, on which port it should forward the packet. Thus, if the downstream switch performs other functions that are dependent on knowing the destination port (e.g., arbitration or QoS updating), the downstream switch can perform those functions immediately since the port ID was already determined by, and received from, the previous network element.

公开(公告)号：US11832035B2

公开(公告)日：2023-11-28

申请号：US17232207

申请日：2021-04-16

Applicant: XILINX, INC.

Inventor： Aman Gupta ,  Sagheer Ahmad ,  Ygal Arbel ,  Abbas Morshed ,  Eun Mi Kim

IPC: H04Q3/00 ,  G06F13/16 ,  G06F13/40

CPC classification number: H04Q3/0004 ,  G06F13/1668 ,  G06F13/4027

Abstract: Embodiments herein describe an integrated circuit that includes a NoC with at least two levels of switching: a sparse network and a non-blocking network. In one embodiment, the non-blocking network is a localized interconnect that provides an interface between the sparse network in the NoC and a memory system that requires additional bandwidth such as HBM2/3 or DDR5. Hardware elements connected to the NoC that do not need the additional benefits provided by the non-blocking network can connect solely to the sparse network. In this manner, the NoC provides a sparse network (which has a lower density of switching elements) for providing communication between lower bandwidth hardware elements and a localized non-blocking network for facilitating communication between the sparse network and higher bandwidth hardware elements.

公开(公告)号：US12111784B2

公开(公告)日：2024-10-08

申请号：US17959903

申请日：2022-10-04

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Abbas Morshed ,  Sagheer Ahmad

IPC: G06F13/40

CPC classification number: G06F13/4059 ,  G06F13/4022

Abstract: Embodiments herein describe a NoC where its internal switches have buffers with pods that can be assigned to different virtual channels. A subset of the pods in a buffer can be grouped together to form a VC. In this manner, different pod groups in a buffer can be assigned to different VCs (or to different types of NoC data units), where VCs that transmit wider data units can be assigned more pods than VCs that transmit narrower data units.

公开(公告)号：US11714779B2

公开(公告)日：2023-08-01

申请号：US16830142

申请日：2020-03-25

Applicant: XILINX, INC.

Inventor： Abbas Morshed ,  Ygal Arbel ,  Eun Mi Kim

IPC: G06F15/78 ,  G06F5/10 ,  G06F9/38 ,  G06F13/40

CPC classification number: G06F15/7825 ,  G06F5/10 ,  G06F9/38 ,  G06F13/4027 ,  G06F2205/064 ,  G06F2213/0038

Abstract: Embodiments herein describe a SoC that includes a NoC that supports both strict and relax ordering requests. That is, some applications may require strict ordering where requests transmitted from the same ingress logic to different egress logic blocks are performed sequentially. However, other applications may not require strict ordering, such as interleaved writes to memory. In those applications, relax ordering can be used were the same ingress logic block can transmit multiple requests to different egress logic blocks in parallel. For example, an ingress logic block may receive a first request that is indicated as being a relaxed ordered request. After transmitting the request to an egress logic block, the ingress logic block may receive a second request. The ingress logic block can transmit the second request to a different egress logic block without waiting for a response for the first request.