公开(公告)号：US20230222082A1

公开(公告)日：2023-07-13

申请号：US17574342

申请日：2022-01-12

Applicant: XILINX, INC.

Inventor： Jaideep DASTIDAR ,  David James RIDDOCH ,  Steven Leslie POPE

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4265 ,  G06F13/1684

Abstract: Embodiments herein describe end-to-end bindings to create zones that extend between different components in a SoC, such as an I/O gateway, a processor subsystem, a NoC, storage and data accelerators, programmable logic, etc. Each zone can be assigned to a different domain that is controlled by a tenant such as an external host, or software executing on that host. Embodiments herein create end-to-end bindings between acceleration engines, I/O gateways, and embedded cores in SoCs. Instead of these components being treated as disparate monolithic components, the bindings divide up the hardware and memory resources across components that make up the SoC, into different zones. Those zones in turn can have unique bindings to multiple tenants. The bindings can be configured in bridges between components to divide resources into the zones to enable tenants of those zones to have dedicated available resources that are secure from the other tenants.

公开(公告)号：US20230224261A1

公开(公告)日：2023-07-13

申请号：US17571292

申请日：2022-01-07

Applicant: XILINX, INC.

Inventor： Steven Leslie POPE ,  Derek Edward ROBERTS ,  Dmitri KITARIEV ,  Neil Duncan TURTON ,  David James RIDDOCH ,  Ripduman SOHAN ,  Stephan DIESTELHORST

IPC: H04L49/00 ,  H04L49/25 ,  H04L49/20 ,  H04L49/90 ,  G06F13/28

CPC classification number: H04L49/30 ,  H04L49/25 ,  H04L49/20 ,  H04L49/90 ,  G06F13/28

Abstract: A network interface device has data path circuitry configured to cause data to be moved into and/or out of the network interface device. The data path circuitry comprises: first circuitry for providing one or more data processing operations; and interface circuitry supporting channels. The channels comprises command channels receiving command information from a plurality of data path circuitry user instances, event channels providing respective command completion information to the plurality of data path user instances; and data channels providing the associated data.

公开(公告)号：US20220292184A1

公开(公告)日：2022-09-15

申请号：US17199200

申请日：2021-03-11

Applicant: XILINX, INC.

Inventor： Steven Leslie POPE ,  Derek Edward ROBERTS ,  Dmitri KITARIEV ,  Neil Duncan TURTON ,  David James RIDDOCH ,  Ripduman SOHAN

IPC: G06F21/53 ,  H04L29/06 ,  G06F21/57

Abstract: A network interface device comprises a first area of trust comprising a first part of the network interface device, the first part comprising one or more first kernels. A second area of trust comprising a second part of the network interface device different to said first part is provided, the second part comprising one or more second kernels. A communication link is provided between the first area of trust and the second area of trust. At least one of the first and second areas of trust is provided with isolation circuitry configured to control which data which is passed to the other of the first and second areas via the communication link.

公开(公告)号：US20220414028A1

公开(公告)日：2022-12-29

申请号：US17357083

申请日：2021-06-24

Applicant: XILINX, INC.

Inventor： Steven Leslie POPE ,  Derek Edward ROBERTS ,  Dmitri KITARIEV ,  Neil Duncan TURTON ,  David James RIDDOCH ,  Ripduman SOHAN

IPC: G06F13/16 ,  G06F13/28 ,  G11C7/10

Abstract: A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.

公开(公告)号：US20240345979A1

公开(公告)日：2024-10-17

申请号：US18642714

申请日：2024-04-22

Applicant: XILINX, INC.

Inventor： Steven Leslie POPE ,  Derek Edward ROBERTS ,  Dmitri KITARIEV ,  Neil Duncan TURTON ,  David James RIDDOCH ,  Ripduman SOHAN

IPC: G06F13/40 ,  G06F9/48

CPC classification number: G06F13/4068 ,  G06F9/4881

Abstract: A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first upstream data path entity and from a first data processing entity implemented in programmable circuitry via a data ingress interface of the first hub. The first data processing engine is configured to receive data from the first hub, process the received data and output the processed data to the second hub arranged downstream of first data processing engine.

公开(公告)号：US20240274162A1

公开(公告)日：2024-08-15

申请号：US18109229

申请日：2023-02-13

Applicant: XILINX, INC.

Inventor： Jaideep DASTIDAR ,  David James RIDDOCH ,  Steven Leslie POPE

IPC: G11C7/10 ,  G11C7/24

CPC classification number: G11C7/1039 ,  G11C7/24

Abstract: An integrated circuit (IC) device includes functional circuits and multiple communication paths, which may include a first communication path through the functional circuits and a second communication path to permit the functional circuits to share information through a buffer and/or to bypass a subset of the functional circuits and a corresponding portion of the first communication path. The IC device may include a variety of protocol-specific interface circuits (ASIC and/or configurable circuitry) for respective IP blocks, and a controller that selectively directs traffic through the various communication paths. The controller may include a set of domain-specific OpCodes that link various subsets/combinations of the protocol-specific interface circuits as respective communication paths. The IC device may include multiple blocks of circuitry, each including a respective set of domain-specific circuitry (e.g., host-domain, network domain, RF domain, and/or data processing domain), and respective sets of OpCodes.

公开(公告)号：US20220292042A1

公开(公告)日：2022-09-15

申请号：US17199197

申请日：2021-03-11

Applicant: XILINX, INC.

Inventor： Steven Leslie POPE ,  Derek Edward ROBERTS ,  Dmitri KITARIEV ,  Neil Duncan TURTON ,  David James RIDDOCH ,  Ripduman SOHAN

IPC: G06F13/40 ,  G06F9/48

Abstract: A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first upstream data path entity and from a first data processing entity implemented in programmable circuitry via a data ingress interface of the first hub. The first data processing engine is configured to receive data from the first hub, process the received data and output the processed data to the second hub arranged downstream of first data processing engine.

公开(公告)号：US20250023808A1

公开(公告)日：2025-01-16

申请号：US18221617

申请日：2023-07-13

Applicant: XILINX, INC.

Inventor： David James RIDDOCH ,  Derek Edward ROBERTS ,  Kieran MANSLEY ,  Steven Leslie POPE ,  Sebastian TURULLOLS

IPC: H04L43/103 ,  H04L67/1097

Abstract: Embodiments herein describe a host that polls a network adapter to receive data from a network. That is, the host/CPU/application thread polls the network adapter (e.g., the network card, NIC, or SmartNIC) to determine whether a packet has been received. If so, the host informs the network adapter to store the packet (or a portion of the packet) in a CPU register. If the requested data has not yet been received by the network adapter from the network, the network adapter can delay the responding to the request to provide extra time for the adapter to receive the data from the network.

公开(公告)号：US20240220440A1

公开(公告)日：2024-07-04

申请号：US18090222

申请日：2022-12-28

Applicant: XILINX, INC.

Inventor： Steven Leslie POPE ,  Derek Edward ROBERTS ,  David James RIDDOCH ,  Ripduman Singh SOHAN

IPC: G06F13/42 ,  G06F9/455

CPC classification number: G06F13/42 ,  G06F9/45558 ,  G06F2009/45595

Abstract: A network interface device comprises at least one processor configured to validate at least a part of a context associated with a queue pair, the context being fetched from a memory on a host device.

公开(公告)号：US20240214111A1

公开(公告)日：2024-06-27

申请号：US18086528

申请日：2022-12-21

Applicant: XILINX, INC.

Inventor： Steven Leslie POPE ,  Derek Edward ROBERTS ,  David James RIDDOCH ,  Ripduman Singh SOHAN

IPC: H04L1/00 ,  H04L1/1829

CPC classification number: H04L1/0083 ,  H04L1/0045 ,  H04L1/1858

Abstract: A network interface device comprises circuitry to add a frame check sequence value a data packet to be transmitted onto a network. The data packet with the frame check sequence value is stored in memory. Media access control layer circuitry reads the data packet from the memory and determines if the frame check sequence value is correct. When it is note correct, it is determined that the data in the data packet is corrupted.