公开(公告)号：US20250036848A1

公开(公告)日：2025-01-30

申请号：US18227225

申请日：2023-07-27

Applicant: XILINX, INC.

Inventor： Aashish TRIPATHI ,  Sundeep Ram Gopal AGARWAL ,  Ashit DEBNATH ,  Atreyee SAHA ,  Praful JAIN

IPC: G06F30/398 ,  G06F30/392

Abstract: A method for predicting voltage drop on a power delivery network of a 3D stacked device includes receiving a spatial power distribution map of a plurality of semiconductor dies of the 3D stacked device, receiving a spatial power source node location map for a plurality of power source nodes coupled to the 3D stacked device, dividing vertically the spatial power distribution map and the spatial power source node location map into overlapping windows, determining a voltage drop map in each of the windows based on the divided spatial power distribution map and the divided spatial power source node location map, and combining the voltage drop map in each of the windows to form a composite voltage drop map.

公开(公告)号：US20240194645A1

公开(公告)日：2024-06-13

申请号：US18079631

申请日：2022-12-12

Applicant: XILINX, INC.

Inventor： Jay T. YOUNG ,  Davis Boyd MOORE ,  Sundeep Ram Gopal AGARWAL ,  Brian C. GAIDE

IPC: H01L25/065 ,  G11C5/02 ,  G11C5/06 ,  H01L23/48 ,  H01L27/02 ,  H01L27/06

CPC classification number: H01L25/0657 ,  G11C5/025 ,  G11C5/063 ,  H01L23/481 ,  H01L27/0207 ,  H01L27/0688 ,  H01L2225/06506

Abstract: An integrated circuit (IC) device includes a block of integrated circuitry that includes functional circuitry and configurable interface circuitry. The configurable interface circuitry includes output circuitry that routes a node of the functional circuitry to an output node of the block, and input circuitry that selectively routes the output node of the block or an input node of the block to the functional circuitry. The output circuitry may route a selectable subset of multiple nodes of the functional circuitry to respective output nodes of the block, and the input circuitry may be configured to route the output nodes of the block back to the functional circuitry in the absence of an adjacent block (e.g., to repurpose the output circuitry), or in addition to interfacing with the adjacent block.