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公开(公告)号:US20150340330A1
公开(公告)日:2015-11-26
申请号:US14715445
申请日:2015-05-18
Applicant: XINTEC INC.
Inventor: Geng-Peng PAN , Yi-Ming CHANG , Chia-Sheng LIN
IPC: H01L23/00 , H01L21/033 , H01L21/302 , H01L23/48 , H01L21/268
CPC classification number: H01L24/03 , H01L21/0273 , H01L21/0334 , H01L21/268 , H01L21/302 , H01L21/48 , H01L21/481 , H01L21/76898 , H01L23/481 , H01L24/05 , H01L2224/0231 , H01L2224/02371 , H01L2224/02372 , H01L2224/03831 , H01L2224/05017 , H01L2224/05024 , H01L2224/05025 , H01L2224/05557 , H01L2224/0557 , H01L2924/00014
Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first isolation layer is formed on a first surface of a wafer substrate. A conductive pad is formed on the first isolation layer. A hollow region through the first surface and a second surface of the wafer substrate is formed, such that the first isolation layer is exposed through the hollow region. A laser etching treatment is performed on the first isolation layer that is exposed through the hollow region, such that a first opening is formed in the first isolation layer, and a concave portion exposed through the first opening is formed in the conductive pad.
Abstract translation: 半导体结构的制造方法包括以下步骤。 在晶片衬底的第一表面上形成第一隔离层。 导电焊盘形成在第一隔离层上。 形成穿过第一表面的中空区域和晶片衬底的第二表面,使得第一隔离层通过中空区域露出。 对通过中空区域暴露的第一隔离层进行激光蚀刻处理,使得在第一隔离层中形成第一开口,并且在导电焊盘中形成通过第一开口暴露的凹部。
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公开(公告)号:US20170213802A1
公开(公告)日:2017-07-27
申请号:US15481355
申请日:2017-04-06
Applicant: XINTEC INC.
Inventor: Geng-Peng PAN , Yi-Ming CHANG , Chia-Sheng LIN
IPC: H01L23/00 , H01L23/48 , H01L21/48 , H01L21/768 , H01L21/027 , H01L21/268
CPC classification number: H01L24/03 , H01L21/0273 , H01L21/0334 , H01L21/268 , H01L21/302 , H01L21/48 , H01L21/481 , H01L21/76805 , H01L21/76898 , H01L23/481 , H01L24/05 , H01L2224/0231 , H01L2224/02371 , H01L2224/02372 , H01L2224/03831 , H01L2224/05017 , H01L2224/05024 , H01L2224/05025 , H01L2224/05557 , H01L2224/0557 , H01L2924/00014
Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first isolation layer is formed on a first surface of a wafer substrate. A conductive pad is formed on the first isolation layer. A hollow region through the first surface and a second surface of the wafer substrate is formed, such that the first isolation layer is exposed through the hollow region. A laser etching treatment is performed on the first isolation layer that is exposed through the hollow region, such that a first opening is formed in the first isolation layer, and a concave portion exposed through the first opening is formed in the conductive pad.
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