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1.发明授权Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing 有权具有浮置栅极，控制栅极，选择栅极和具有悬垂在浮动栅极上的擦除栅极的分流门非易失性闪存单元，阵列和制造方法公开(公告)号：US07927994B1
公开(公告)日：2011-04-19
申请号：US12961193
申请日：2010-12-06
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
IPC分类号： H01L21/4763
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
摘要翻译： 改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间 和底物中的第二区域。 单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。 擦除栅极具有在浮动栅极上延伸的突出端。 悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。
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2.发明申请Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing 审中-公开分闸门非挥发性闪存单元，具有浮动栅极，控制栅极，选择栅极和具有悬垂在浮栅上的擦除栅极，阵列和制造方法公开(公告)号：US20090039410A1
公开(公告)日：2009-02-12
申请号：US11834574
申请日：2007-08-06
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
IPC分类号： H01L29/788
CPC分类号： H01L29/42328 , H01L27/11521 , H01L29/40114 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
摘要翻译： 改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间 和底物中的第二区域。 单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。 擦除栅极具有在浮动栅极上延伸的突出端。 悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。
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公开(公告)号：US07868375B2
公开(公告)日：2011-01-11
申请号：US12618632
申请日：2009-11-13
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien Sheng Su , Yaw Wen Hu
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
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4.发明申请SPLIT GATE NON-VOLATILE FLASH MEMORY CELL HAVING A FLOATING GATE, CONTROL GATE, SELECT GATE AND AN ERASE GATE WITH AN OVERHANG OVER THE FLOATING GATE, ARRAY AND METHOD OF MANUFACTURING 有权分离闸门具有浮动门，控制门，选择门和在浮动门，阵列和制造方法上的过滤器的非挥发性闪存存储单元公开(公告)号：US20110076816A1
公开(公告)日：2011-03-31
申请号：US12961193
申请日：2010-12-06
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
摘要翻译： 改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间 和底物中的第二区域。 单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。 擦除栅极具有在浮动栅极上延伸的突出端。 悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。
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5.发明申请Split Gate Non-volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing 审中-公开具有浮动门的分闸门非易失性闪存单元，控制门，选择门和具有悬浮在浮动门上的擦除门，阵列和制造方法公开(公告)号：US20110127599A1
公开(公告)日：2011-06-02
申请号：US13023443
申请日：2011-02-08
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
IPC分类号： H01L29/788
CPC分类号： H01L29/42328 , H01L27/11521 , H01L29/40114 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
摘要翻译： 改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间 和底物中的第二区域。 单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。 擦除栅极具有在浮动栅极上延伸的突出端。 悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。
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6.发明申请Split Gate Non-Volatile Flash Memory Cell Having a Floating Gate, Control Gate, Select Gate and an Erase Gate with an Overhang Over the Floating Gate, Array and Method of Manufacturing 有权具有浮动门的分流门非易失性闪存单元，控制栅极，选择栅极和擦除栅极，在浮动栅极上的突出，阵列和制造方法公开(公告)号：US20100054043A1
公开(公告)日：2010-03-04
申请号：US12618632
申请日：2009-11-13
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
IPC分类号： G11C16/04 , H01L21/336 , G11C11/34 , H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
摘要翻译： 改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间 和底物中的第二区域。 单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。 擦除栅极具有在浮动栅极上延伸的突出端。 悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。
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7.发明授权Self-aligned stack gate structure for use in a non-volatile memory array and a method of forming such structure 有权用于非易失性存储器阵列的自对准堆叠栅极结构以及形成这种结构的方法公开(公告)号：US09330922B2
公开(公告)日：2016-05-03
申请号：US13414400
申请日：2012-03-07
申请人： Willem-Jan Toren , Xian Liu , Gerhard Metzger-Brueckl , Nhan Do , Stephan Wege , Nadia Miridi , Chien-Sheng Su , Cecile Bernardi , Liz Cuevas , Florence Guyot , Yueh-Hsin Chen , Henry Om'mani , Mandana Tadayoni
发明人： Willem-Jan Toren , Xian Liu , Gerhard Metzger-Brueckl , Nhan Do , Stephan Wege , Nadia Miridi , Chien-Sheng Su , Cecile Bernardi , Liz Cuevas , Florence Guyot , Yueh-Hsin Chen , Henry Om'mani , Mandana Tadayoni
IPC分类号： H01L29/788 , H01L21/28 , H01L27/115 , H01L21/762
CPC分类号： H01L29/66545 , H01L21/28273 , H01L21/28282 , H01L21/76283 , H01L27/11521 , H01L27/11568
摘要： A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.
摘要翻译： 用于非易失性存储器阵列的堆叠栅极结构具有半导体衬底，该半导体衬底具有多个基本上平行的间隔开的有源区，每个有源区具有沿第一方向的轴。 在垂直于第一方向的第二方向上，第一绝缘材料位于每个堆叠栅极结构之间。 每个堆叠栅极结构在有源区域上具有第二绝缘材料，在第二绝缘材料上方的电荷保持栅极，电荷保持栅极上方的第三绝缘材料以及位于第三绝缘材料上的控制栅极的第一部分。 控制栅极的第二部分在控制栅极的第一部分之上，并且与第一部分相邻并且在第二方向上延伸。 第四绝缘材料位于控制栅极的第二部分之上。
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8.发明申请Self-Aligned Stack Gate Structure For Use In A Non-volatile Memory Array And A Method Of Forming Such Structure 有权用于非易失性存储器阵列的自对准堆栈门结构和形成这种结构的方法公开(公告)号：US20130234223A1
公开(公告)日：2013-09-12
申请号：US13414400
申请日：2012-03-07
申请人： Willem-Jan Toren , Xian Liu , Gerhard Metzger-Brueckl , Nhan Do , Stephan Wege , Nadia Miridi , Chien-Sheng Su , Cecile Bernardi , Liz Cuevas , Florence Guyot , Yueh-Hsin Chen , Henry Om'mani , Mandana Tadayoni
发明人： Willem-Jan Toren , Xian Liu , Gerhard Metzger-Brueckl , Nhan Do , Stephan Wege , Nadia Miridi , Chien-Sheng Su , Cecile Bernardi , Liz Cuevas , Florence Guyot , Yueh-Hsin Chen , Henry Om'mani , Mandana Tadayoni
IPC分类号： H01L27/088 , H01L21/762
CPC分类号： H01L29/66545 , H01L21/28273 , H01L21/28282 , H01L21/76283 , H01L27/11521 , H01L27/11568
摘要： A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.
摘要翻译： 用于非易失性存储器阵列的堆叠栅极结构具有半导体衬底，该半导体衬底具有多个基本上平行的间隔开的有源区，每个有源区具有沿第一方向的轴。 在垂直于第一方向的第二方向上，第一绝缘材料位于每个堆叠栅极结构之间。 每个堆叠栅极结构在有源区域上具有第二绝缘材料，在第二绝缘材料上方的电荷保持栅极，电荷保持栅极上方的第三绝缘材料以及位于第三绝缘材料上的控制栅极的第一部分。 控制栅极的第二部分在控制栅极的第一部分之上，并且与第一部分相邻并且在第二方向上延伸。 第四绝缘材料位于控制栅极的第二部分之上。
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9.发明授权Method of forming a memory cell by reducing diffusion of dopants under a gate 有权通过减少栅极下掺杂剂的扩散形成存储单元的方法公开(公告)号：US08785307B2
公开(公告)日：2014-07-22
申请号：US13593448
申请日：2012-08-23
申请人： Xian Liu , Mandana Tadayoni , Chien-Sheng Su , Nhan Do
发明人： Xian Liu , Mandana Tadayoni , Chien-Sheng Su , Nhan Do
IPC分类号： H01L21/04
CPC分类号： H01L27/11521 , H01L21/26586 , H01L21/28273 , H01L29/42328 , H01L29/66825 , H01L29/7881
摘要： A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees.
摘要翻译： 形成存储单元的方法包括在衬底上形成导电浮栅，在浮置栅极上形成导电控制栅极，在浮栅的一侧横向形成导电擦除栅极，并横向形成导电选择栅极 一侧的浮动门。 在形成浮置和选择栅极之后，该方法包括使用注入工艺将掺杂剂注入到选择栅极下方的沟道区域的一部分中，所述注入工艺以相对于衬底表面小于 九十度，大于零度。
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10.发明授权Non-volatile memory device with plural reference cells, and method of setting the reference cells 有权具有多个参考单元的非易失性存储器件，以及设置参考单元的方法公开(公告)号：US08780639B2
公开(公告)日：2014-07-15
申请号：US13466878
申请日：2012-05-08
申请人： Xian Liu , Michael James Heinz , Eugene Jinglun Tam , Michael K. Doan , Alexander Kotov , Tho Ngoc Dang , Jack Edward Frayer , Jung Hee Yun , Thuan T. Vu
发明人： Xian Liu , Michael James Heinz , Eugene Jinglun Tam , Michael K. Doan , Alexander Kotov , Tho Ngoc Dang , Jack Edward Frayer , Jung Hee Yun , Thuan T. Vu
IPC分类号： G11C16/06
CPC分类号： G11C7/00 , G11C7/14 , G11C11/5628 , G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.
摘要翻译： 非易失性存储器件具有非易失性存储器单元的阵列，第一多个非易失性存储器参考单元，每个参考单元能够被编程到与其它参考单元不同的参考电平; 和第二多个比较器。 每个比较器可从第一组非易失性存储器参考单元中的一个连接到非易失性存储器单元阵列中的第三多个存储器单元中的一个。
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