Bimodal digital-to-analog conversion
    1.
    发明授权
    Bimodal digital-to-analog conversion 有权
    双模数模转换

    公开(公告)号:US08922412B1

    公开(公告)日:2014-12-30

    申请号:US13874040

    申请日:2013-04-30

    Applicant: Xilinx, Inc.

    CPC classification number: H03M1/0604 H03M1/662 H03M1/742

    Abstract: An apparatus relating generally to digital-to-analog conversion is disclosed. In such an apparatus, a digital-to-analog converter (“DAC”) device includes a source DAC and a sink DAC selectively coupled to one another. The source DAC provides a first bias to the sink DAC in a sink mode, and the sink DAC provides a second bias to the source DAC in a source mode.

    Abstract translation: 公开了一般涉及数模转换的装置。 在这种装置中,数模转换器(“DAC”)装置包括一个选择性地耦合到彼此的源DAC和信宿DAC。 源DAC在宿模式中向宿DAC提供第一偏置,并且宿DAC在源模式中向源DAC提供第二偏置。

    Differential level shifter for improving common mode rejection ratio
    2.
    发明授权
    Differential level shifter for improving common mode rejection ratio 有权
    差分电平转换器,用于提高共模抑制比

    公开(公告)号:US09093987B1

    公开(公告)日:2015-07-28

    申请号:US13630486

    申请日:2012-09-28

    Applicant: Xilinx, Inc.

    CPC classification number: H03K3/012 H03K19/018521

    Abstract: A differential level shifter includes: a first PMOS transistor, wherein a source/drain of the first PMOS transistor is coupled to a first CMOS signal, a gate of the first PMOS transistor is coupled to ground, and another source/drain of the first PMOS transistor is coupled to a first output node; a second PMOS transistor, wherein a source/drain of the second PMOS transistor is coupled to a second CMOS signal, a gate of the second PMOS transistor is coupled to ground, and another source/drain of the second PMOS transistor is coupled to a second output node; and a shift component coupled between the first output node and the second output node.

    Abstract translation: 差分电平移位器包括:第一PMOS晶体管,其中第一PMOS晶体管的源极/漏极耦合到第一CMOS信号,第一PMOS晶体管的栅极耦合到地,并且第一PMOS的另一个源极/漏极 晶体管耦合到第一输出节点; 第二PMOS晶体管,其中第二PMOS晶体管的源极/漏极耦合到第二CMOS信号,第二PMOS晶体管的栅极耦合到地,并且第二PMOS晶体管的另一个源极/漏极耦合到第二PMOS晶体管的第二 输出节点; 以及耦合在所述第一输出节点和所述第二输出节点之间的移位分量。

Patent Agency Ranking