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公开(公告)号：US11881884B2
公开(公告)日：2024-01-23
申请号：US17698871
申请日：2022-03-18
Applicant: XILINX, INC.
Inventor： Hari Bilash Dubey , Lanka Sasi Rama Subrahmanyam
CPC classification number: H04B1/18 , H04B1/1676
Abstract: Receiver circuitry for an input/output device includes first stage circuitry and second stage. The first stage circuitry has a first input to receive an input signal, voltage adjustment circuitry, and differential amplifier circuitry. The first stage circuitry is coupled to the first input and has a transistor pair to receive the input signal, and adjust a voltage value of the input signal to generate an adjusted signal. The differential amplifier circuitry receives the adjusted signal and a reference signal, and generates a first differential signal and a second differential signal. The second stage circuitry receives the first differential signal and the second differential signal, and generates an output signal based on the first differential signal and the second differential signal.
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公开(公告)号：US10608618B1
公开(公告)日：2020-03-31
申请号：US16022206
申请日：2018-06-28
Applicant: Xilinx, Inc.
Inventor： Sabarathnam Ekambaram , Milind Goel , Hari Bilash Dubey
IPC: H03K3/00 , H03K3/356 , H03K19/017
Abstract: A method, non-transitory computer readable medium, and circuit for wide range voltage translation using monostable multi-vibrator feedback are disclosed. The circuit includes a bias generation segment and a voltage translator to shift a voltage level of a signal from a first voltage domain of a digital system to a second voltage domain of the digital system. The bias generation segment is configured to detect a voltage range of the second voltage domain and to configure the voltage translator responsive to the voltage range. The voltage translator is configured to directly shift the voltage level of the signal to the second voltage domain. The second voltage domain has voltage levels that are higher than a maximum voltage that can be tolerated by transistors in the digital system.
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公开(公告)号：US11750185B2
公开(公告)日：2023-09-05
申请号：US17482336
申请日：2021-09-22
Applicant: XILINX, INC.
Inventor： Siva Charan Nimmagadda , Xiaobao Wang , Vinit Shah , Sabarathnam Ekambaram , Hari Bilash Dubey
CPC classification number: H03K5/1565 , G11C7/222 , H03K5/134 , H03K5/135
Abstract: Examples describe a duty cycle correction circuit for correcting duty cycle distortion from memory. One example is an integrated circuit for correcting an input clock signal. The integrated circuit includes a first leg circuit and a second leg circuit. The first leg circuit and the second leg circuit both comprise a charging circuit and a discharging circuit. Each charging circuit comprises a first plurality of transistors and each discharging circuit comprises a second plurality of transistors. The charging circuit is coupled to the discharging circuit in series. A number of transistors of the first plurality of transistors in the first leg circuit is different from a number of transistors of the first plurality of transistors in the second leg circuit.
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公开(公告)号：US10484041B2
公开(公告)日：2019-11-19
申请号：US15703800
申请日：2017-09-13
Applicant: Xilinx, Inc.
Inventor： Sabarathnam Ekambaram , VSS Prasad Babu Akurathi , Milind Goel , Hari Bilash Dubey
IPC: H04B1/00 , H04B1/58 , H04B1/44 , H04B1/04 , H03K19/0185
Abstract: An example receiver includes: a pad splitter circuit coupled to a pad, the pad splitter circuit configured to generate a first logic signal and a second logic signal; a wide-range receiver coupled to the pad splitter circuit to receive the first and second logic signals, the wide-range receiver comprising a combination of a first Schmitt trigger receiver and a second Schmitt trigger receiver; a control circuit coupled to the pad splitter circuit and the wide-range receiver; and a bias generator circuit coupled to the pad splitter circuit and the wide-range receiver.
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公开(公告)号：US20190081656A1
公开(公告)日：2019-03-14
申请号：US15703800
申请日：2017-09-13
Applicant: Xilinx, Inc.
Inventor： Sabarathnam Ekambaram , VSS Prasad Babu Akurathi , Milind Goel , Hari Bilash Dubey
CPC classification number: H04B1/586 , H03K19/018521 , H04B1/005 , H04B1/0475 , H04B1/44
Abstract: An example receiver includes: a pad splitter circuit coupled to a pad, the pad splitter circuit configured to generate a first logic signal and a second logic signal; a wide-range receiver coupled to the pad splitter circuit to receive the first and second logic signals, the wide-range receiver comprising a combination of a first Schmitt trigger receiver and a second Schmitt trigger receiver; a control circuit coupled to the pad splitter circuit and the wide-range receiver; and a bias generator circuit coupled to the pad splitter circuit and the wide-range receiver.
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Patent Agency Ranking
公开(公告)号：US09998120B1
公开(公告)日：2018-06-12
申请号：US15448494
申请日：2017-03-02
Applicant: Xilinx, Inc.
Inventor： Sabarathnam Ekambaram , Hari Bilash Dubey
IPC: H03K19/0175 , H03K19/094 , H03K19/0185 , H03K19/177
CPC classification number: H03K19/018521 , H03K19/017581 , H03K19/1776
Abstract: A circuit for shifting an input common mode voltage is described. The circuit comprises a first current path configured to generate a first current between a reference voltage and a ground potential, the first current path having a first output; a second current path configured to generate a second current between the reference voltage and the ground potential, the second current path having a second output; a first bias current control circuit coupled to the first current path and the second current path, wherein the first bias control circuit is configured to receive the input voltage to control the current in the first current path and the second current path; and a second bias current control circuit coupled to the first current path and the second current path, wherein the second bias control circuit is configured to receive the input voltage to control the current in the first current path and the second current path. A method of shifting an input common mode voltage is also described.
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公开(公告)号：US12153458B2
公开(公告)日：2024-11-26
申请号：US18082921
申请日：2022-12-16
Applicant: XILINX, INC.
IPC: H03K17/687 , G05F1/56
Abstract: An input/output (I/O) buffer is implemented without an auxiliary power supply (VCCAUX). The input/output (I/O) buffer includes a connection to a VCCO power supply, a connection to a VCCINT power supply, a connection to a reference voltage, and a VCCO detection circuit coupled to a bias generation circuit. Further, the I/O buffer includes a transmitter circuit coupled to the bias generation circuit, and a receiver circuit coupled to an I/O pad.
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公开(公告)号：US11777489B1
公开(公告)日：2023-10-03
申请号：US17747387
申请日：2022-05-18
Applicant: Xilinx, Inc.
Inventor： Hari Bilash Dubey , Milind Goel , Venkata Siva Satya Prasad Babu Akurathi , Sabarathnam Ekambaram , Sasi Rama Subrahmanyam Lanka
IPC: H03K17/22 , H03K17/10 , H03K19/00 , H03K19/003
CPC classification number: H03K17/223 , H03K17/102 , H03K19/0013 , H03K19/00315
Abstract: A disclosed circuit arrangement detects the supply voltage level to the “device” (SoC, chip, SiP, etc.) and adjusts bias voltages to receiver and transmitter circuits of the device to levels suitable for the device in response to the supply voltage ramping-up during a power-on reset (“POR”) sequence. The circuitry holds the receiver output at a constant logic value while the supply voltage is ramping up and the POR signal is asserted. The disclosed circuitry also protects the transceiver as the voltage domain of the input signal is unknown and the voltage between any two terminals of a transistor of the transceiver cannot exceed a certain level.
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公开(公告)号：US11664800B1
公开(公告)日：2023-05-30
申请号：US16511925
申请日：2019-07-15
Applicant: Xilinx, Inc.
Inventor： VSS Prasad Babu Akurathi , Sabarathnam Ekambaram , Sasi Rama S. Lanka , Hari Bilash Dubey , Milind Goel
IPC: H03K17/687
CPC classification number: H03K17/6872
Abstract: A circuit for implementing an input/output connection in an integrated circuit device is described. The circuit comprises a pull-up circuit comprising a first plurality of transistors coupled in series, wherein a gate of a first transistor of the first plurality of transistors is configured to receive a first dynamic bias signal; a pull-down circuit comprising a second plurality of transistors coupled in series, the pull-down circuit being coupled to the pull-up circuit at an output node, wherein a gate of a first transistor of the second plurality of transistors is configured to receive a second dynamic bias signal; and an input/output contact coupled to the output node. A circuit for implementing an input/output connection in an integrated circuit device including a splitter circuit for receiving an input signal on an input pad is also described. A method of implementing an input/output connection in an integrated circuit device is also described.
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公开(公告)号：US11581888B1
公开(公告)日：2023-02-14
申请号：US17555192
申请日：2021-12-17
Applicant: XILINX, INC.
Inventor： Hari Bilash Dubey
IPC: H03K17/22
Abstract: A power-on reset circuit with reduced detection time. One example power-on reset circuit generally includes a voltage sensing circuit having an input coupled to a first power supply rail; a variable resistance component having a control input coupled to an output of the voltage sensing circuit and having a first terminal coupled to the first power supply rail; and an amplitude detection circuit having a first input coupled to the first power supply rail and having a second input coupled to a second terminal of the variable resistance component, the amplitude detection circuit being configured to generate a power-on reset signal at an output of the amplitude detection circuit based on a difference between a first voltage of the first power supply rail and a second voltage at the second terminal of the variable resistance component.
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