公开(公告)号：US11386020B1

公开(公告)日：2022-07-12

申请号：US16808054

申请日：2020-03-03

Applicant: XILINX, INC.

Inventor： Matthew H. Klein ,  Goran Hk Bilski ,  Juan Jose Noguera Serra ,  Ismed D. Hartanto ,  Sridhar Subramanian ,  Tim Tuan

IPC: G06F15/17 ,  G06F13/16 ,  G06F9/30 ,  H03K19/1776 ,  G06F7/501 ,  G06F15/173

Abstract: Some examples described herein relate to programmable devices that include a data processing engine (DPE) array that permits shifting of where an application is loaded onto DPEs of the DPE array. In an example, a programmable device includes a DPE array. The DPE array includes DPEs and address index offset logic. Each of the DPEs includes a processor core and a memory mapped switch. The processor core is programmable via one or more memory mapped packets routed through the respective memory mapped switch. The memory mapped switches in the DPE array are coupled together to form a memory mapped interconnect network. The address index offset logic is configurable to selectively modify which DPE in the DPE array is targeted by a respective memory mapped packet routed in the memory mapped interconnect network.

公开(公告)号：US10234505B1

公开(公告)日：2019-03-19

申请号：US15443990

申请日：2017-02-27

Applicant: Xilinx, Inc.

Inventor： Banadappa V. Shivaray ,  Ismed D. Hartanto ,  Alex S. Warshofsky ,  Pranjal Chauhan

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3177

Abstract: A disclosed integrated circuit includes first and second clock generation circuits, a stagger circuit, and a plurality of scan chains. The first clock generation circuit receives a first clock signal and generates a first set of clock pulses having a first frequency in response to receipt of a first clock trigger signal and a first enable signal. The second clock generation circuit receives a second clock signal and generates a second set of clock pulses having a second frequency in response to receipt of a second clock trigger signal and a second enable signal. The stagger circuit generates the first and second clock trigger signals from the global trigger signal at different times. The first set of clock pulses are staggered relative to the second set of clock pulses. The plurality of scan chains test functionality of logic circuitry within the IC chip using the first and second set of clock pulses.

公开(公告)号：US09600018B1

公开(公告)日：2017-03-21

申请号：US14300159

申请日：2014-06-09

Applicant: Xilinx, Inc.

Inventor： Amitava Majumdar ,  Balakrishna Jayadev ,  Ismed D. Hartanto

IPC: G06F1/00 ,  G06F1/12 ,  G06F1/06 ,  G06F1/10

CPC classification number: G06F1/10 ,  G06F1/04 ,  G06F1/06 ,  G06F1/12

Abstract: Methods and circuits for performing a clock-stop process of a circuit are disclosed. For example, a circuit includes a clock group having a first clock domain, a first clock multiplexer, a first synchronizer and a controller. The controller is configured to initiate a clock stop process of the circuit by sending an alternative mode signal to the first synchronizer. The first synchronizer is configured to synchronize the alternative mode signal to a clock of the first clock domain and is further configured to output, to a select line of the first clock multiplexer, the alternative mode signal that is synchronized to the clock of the first clock domain. The select line of the first clock multiplexer is for selecting from between an input of the first clock multiplexer for the clock of the first clock domain and an alternative clock input of the first clock multiplexer for an alternative clock signal from the controller.

公开(公告)号：US10969433B1

公开(公告)日：2021-04-06

申请号：US16554059

申请日：2019-08-28

Applicant: XILINX, INC.

Inventor： Rambabu Nerukonda ,  Ismed D. Hartanto ,  Aaron K. Mathew

IPC: G01R31/3185 ,  G06F9/30 ,  G01R31/3177

Abstract: Apparatus and associated methods relate to compacting scan chain output responses of vectors into an on-chip multiple-input shift register (MISR) in the presence of unknown/indeterministic values X in design. In an illustrative example, a system may include a processing engine configured to generate a control signal for a MISR, and the control signal may hold information of what cycle has deterministic output response. The MISR may be configured to compact deterministic output responses of actual scan chain output responses in response to the decoded control signal and compare on-chip MISR signatures with expected MISR signatures to generate pass/fail status of the test. By using the system, unknown/indeterministic values X on the output responses may be blocked from being compacted into the MISR. Accordingly, the on-chip MISR signatures may not be corrupted by the unknown/indeterministic values X, and accuracy of the scan test may be advantageously improved.