公开(公告)号：US09628082B1

公开(公告)日：2017-04-18

申请号：US14321577

申请日：2014-07-01

Applicant: Xilinx, Inc.

Inventor： David S. Smith ,  Xiaobao Wang ,  Arvind R. Bomdica ,  Balakrishna Jayadev

IPC: H03K17/16 ,  H03K19/177 ,  H03K3/01

CPC classification number: H03K19/177 ,  H03K3/01 ,  H03K19/018585

Abstract: An apparatus includes a plurality of adjustable driver circuits having output nodes coupled to a signal line. Each adjustable driver circuit is configured to drive the signal line with a portion of a total drive strength indicated by a value of a binary control signal. The apparatus also includes a delay circuit configured to delay the binary control signal provided to each adjustable driver circuit by a respective time period unique to the adjustable driver circuit.

公开(公告)号：US12237287B2

公开(公告)日：2025-02-25

申请号：US18369115

申请日：2023-09-15

Applicant: XILINX, INC.

Inventor： Ygal Arbel ,  Kenneth Ma ,  Balakrishna Jayadev ,  Sagheer Ahmad

IPC: G11C5/00 ,  G11C5/06 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: Embodiments herein describe a multiple die system that includes an interposer that connects a first die to a second die. Each die has a bump interface structure that is connected to the other structure using traces in the interposer. However, the bump interface structures may have different orientations relative to each other, or one of the interface structures defines fewer signals than the other. Directly connecting the corresponding signals defined by the structures to each other may be impossible to do in the interposer, or make the interposer too costly. Instead, the embodiments here simplify routing in the interposer by connecting the signals in the bump interface structures in a way that simplifies the routing but jumbles the signals. The jumbled signals can then be corrected using reordering circuitry in the dies (e.g., in the link layer and physical layer).

公开(公告)号：US09798352B1

公开(公告)日：2017-10-24

申请号：US14939704

申请日：2015-11-12

Applicant: Xilinx, Inc.

Inventor： Amitava Majumdar ,  Balakrishna Jayadev

IPC: G01R31/317 ,  G01R31/3185 ,  G06F1/10

CPC classification number: G06F1/10 ,  G01R31/31704 ,  G01R31/31705 ,  G01R31/31726 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318583

Abstract: A circuit for implementing a scan chain in an integrated circuit having a clock domain crossing is described. The circuit comprises a first dual-edge storage circuit configured to receive an input signal at a scan input and to receive a first clock signal in a first clock domain at a clock input; a storage element having a data input configured to receive an output of the first dual-edge storage circuit; a second dual-edge storage circuit configured to receive an output of the storage element at a scan input and to receive a second clock signal in a second clock domain at a clock input; and a pulse generator configured to provide, to a clock input of the storage element, a pulse signal having a pulse width selected to enable the second dual-edge storage element to store the output of the first dual-edge storage element.

公开(公告)号：US11784149B1

公开(公告)日：2023-10-10

申请号：US17235843

申请日：2021-04-20

Applicant: XILINX, INC.

Inventor： Ygal Arbel ,  Kenneth Ma ,  Balakrishna Jayadev ,  Sagheer Ahmad

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L24/16 ,  H01L23/5384 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/0651 ,  H01L2924/1434

Abstract: Embodiments herein describe a multiple die system that includes an interposer that connects a first die to a second die. Each die has a bump interface structure that is connected to the other structure using traces in the interposer. However, the bump interface structures may have different orientations relative to each other, or one of the interface structures defines fewer signals than the other. Directly connecting the corresponding signals defined by the structures to each other may be impossible to do in the interposer, or make the interposer too costly. Instead, the embodiments here simplify routing in the interposer by connecting the signals in the bump interface structures in a way that simplifies the routing but jumbles the signals. The jumbled signals can then be corrected using reordering circuitry in the dies (e.g., in the link layer and physical layer).

公开(公告)号：US10659215B1

公开(公告)日：2020-05-19

申请号：US16135653

申请日：2018-09-19

Applicant: Xilinx, Inc.

Inventor： Xiaobao Wang ,  Arvind R. Bomdica ,  Balakrishna Jayadev ,  Richard W. Swanson

IPC: G11C7/00 ,  G11C11/00 ,  H04L7/00 ,  G11C7/22 ,  H03L7/081 ,  G11C7/10 ,  G11C29/50

Abstract: Methods and apparatus relate to a 1-to-2 memory interface deserializer circuit that, in a training mode, independently positions even and odd strobes in respective even and odd data windows. In an illustrative example, the deserializer circuit may receive a data signal that encodes even and odd data streams on the rising (even) and falling (odd) edges of a strobe clock signal. During a training mode, the deserializer circuit may independently determine, for example, an optimal temporal delay for each of the even strobe and the odd strobe. Adjustable delay lines dedicated to each of the even and odd strobe signals may simultaneously detect valid data window edges to permit determination of a desired delay to optimally position the strobe signals. Various embodiments may advantageously reduce jitter associated with asymmetric strobe and/or data signals to achieve a predetermined specification (e.g., timing margins) within the corresponding data windows.

公开(公告)号：US09600018B1

公开(公告)日：2017-03-21

申请号：US14300159

申请日：2014-06-09

Applicant: Xilinx, Inc.

Inventor： Amitava Majumdar ,  Balakrishna Jayadev ,  Ismed D. Hartanto

IPC: G06F1/00 ,  G06F1/12 ,  G06F1/06 ,  G06F1/10

CPC classification number: G06F1/10 ,  G06F1/04 ,  G06F1/06 ,  G06F1/12

Abstract: Methods and circuits for performing a clock-stop process of a circuit are disclosed. For example, a circuit includes a clock group having a first clock domain, a first clock multiplexer, a first synchronizer and a controller. The controller is configured to initiate a clock stop process of the circuit by sending an alternative mode signal to the first synchronizer. The first synchronizer is configured to synchronize the alternative mode signal to a clock of the first clock domain and is further configured to output, to a select line of the first clock multiplexer, the alternative mode signal that is synchronized to the clock of the first clock domain. The select line of the first clock multiplexer is for selecting from between an input of the first clock multiplexer for the clock of the first clock domain and an alternative clock input of the first clock multiplexer for an alternative clock signal from the controller.

公开(公告)号：US10410694B1

公开(公告)日：2019-09-10

申请号：US16048084

申请日：2018-07-27

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Sagheer Ahmad ,  Balakrishna Jayadev

IPC: G11C7/10 ,  G06F11/10 ,  G06F3/06

Abstract: Techniques related to a high bandwidth interface (HBI) for communication between multiple host devices on an interposer are described. In an example, the HBI repurposes a portion of the high bandwidth memory (HBM) interface, such as the physical layer. A computing system is provided. The computing system includes a first host device and at least a second host device. The first host device is a first die on an interposer and the second host device is a second die on the interposer. The first host device and the second host device are interconnected via at least one HBI. The HBI implements a layered protocol for communication between the first host device and the second host device. The layered protocol includes a physical layer protocol that is configured according to a HBM physical layer protocol.