公开(公告)号：US10740210B1

公开(公告)日：2020-08-11

申请号：US15824631

申请日：2017-11-28

Applicant: Xilinx, Inc.

Inventor： Paul R. Schumacher ,  Kumar Deepak ,  Roger Ng ,  David K. Liddell

IPC: G06F9/44 ,  G06F11/34 ,  G06F8/41 ,  G06F7/02 ,  G06F11/36 ,  G06F16/2458

Abstract: Tracing operation of a kernel can include comparing, using a processor, signals of a compiled kernel with a database including compiler generated signals for compute units to determine a list of the signals of the compiled kernel that match the compiler generated signals and generating trace data by emulating the compiled kernel using the processor. The trace data includes values for signals of the compiled kernel collected over time during the emulation. Operational data corresponding to individual compute units of the compiled kernel can be determined from values of the signals of the list within the trace data using the processor. The operational data can be displayed using the processor.

公开(公告)号：US10380313B1

公开(公告)日：2019-08-13

申请号：US15372731

申请日：2016-12-08

Applicant: Xilinx, Inc.

Inventor： Paul R. Schumacher ,  Kumar Deepak ,  Scott Jonas

IPC: G06F17/50

Abstract: Implementing a design for a heterogeneous computing platform can include storing, using a processor, profile data in a memory, wherein the profile data is generated from running the design for the heterogeneous computing platform and wherein the design includes a kernel adapted for hardware acceleration. Compliance of the design with a profile rule may be determined by comparing, using the processor, the profile data accessed from the memory with the profile rule. The profile rule can specify a design requirement for a hardware accelerated implementation of the kernel. Compliance of the design with the profile rule can be indicated, using the processor, based upon the comparing.

公开(公告)号：US11042564B1

公开(公告)日：2021-06-22

申请号：US16145013

申请日：2018-09-27

Applicant: Xilinx, Inc.

Inventor： David K. Liddell ,  Roger Ng ,  Kumar Deepak

IPC: G06F16/26 ,  G06T11/20 ,  G06F9/46 ,  G06F16/248 ,  G06F16/23 ,  G06F3/0484 ,  G06T11/60

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating transaction associations in a waveform display. One of the methods includes receiving data representing a main signal for a selected transaction in a waveform display, the main signal including a plurality of main signal events. A search is performed for data representing one or more side signals associated with the main signal for the selected transaction, each side signal including a plurality of side signal events representing other transactions that are associated with the main signal at a time indicated by a corresponding main signal event. A visual indication is generated within the waveform display of an association between the selected transaction and one or more transactions identified by the one or more side signals associated with the main signal for the selected transaction.

公开(公告)号：US10067854B2

公开(公告)日：2018-09-04

申请号：US15334182

申请日：2016-10-25

Applicant: Xilinx, Inc.

Inventor： Jason Villarreal ,  Kumar Deepak

IPC: G06F9/44 ,  G06F11/36

Abstract: Approaches for debugging include receiving by a hardware debug server, a high-level language (HLL) debugging command for setting a breakpoint in an HLL software specification. The hardware debug server translates the HLL debugging command into a hardware debugging command that specifies a condition of a hardware finite state machine that is representation of the software specification. The hardware debugging command is input to a simulator. The simulator adds a conditional breakpoint on the finite state machine in response to the hardware debugging command and executes a simulation of the finite state machine representation. Execution of the simulation is suspended in response to the detecting the condition in the finite state machine.

公开(公告)号：US11144687B1

公开(公告)日：2021-10-12

申请号：US16370260

申请日：2019-03-29

Applicant: Xilinx, Inc.

Inventor： Pramod Chandraiah ,  Roger Ng ,  Alain Darte ,  Radharamanan Radhakrishnan ,  Peter Frey ,  Kumar Deepak

IPC: G06F30/30

Abstract: Disclosed approaches monitor states of a plurality of sets of a plurality of handshake signals. Each set of handshake signals is associated with a respective one sub-circuit of a plurality of sub-circuits. For each sub-circuit, a beginning of an iteration by the sub-circuit is detected based on states of the plurality of handshake signals of the set associated with the sub-circuit. A graphics object is generated in response to detecting the beginning of the iteration. The graphics object is displayed on a display device and overlaid on a timeline associated with the sub-circuit. The graphics object has a bound that corresponds to the beginning of the iteration. The end of the iteration is detected based on the states of the associated set of handshake signals, and the graphics object is bounded on the timeline to indicate the end of the iteration.

公开(公告)号：US10437949B1

公开(公告)日：2019-10-08

申请号：US15676104

申请日：2017-08-14

Applicant: Xilinx, Inc.

Inventor： Valeria Mihalache ,  Kumar Deepak ,  Saikat Bandyopadhyay

IPC: G06F9/455 ,  G06F17/50

Abstract: Simulating a circuit design can include detecting, using a processor, an assignment for a signal of a circuit design during a delta cycle of a simulation of the circuit design and comparing, using the processor, a range of the assignment for the signal with a range of an existing event for the signal for the delta cycle. In response to determining that the range of the assignment for the signal and the range of the existing event meet a condition, the existing event is updated, using the processor, resulting in a merged event. The merged event is scheduled for execution for the delta cycle using the processor.

公开(公告)号：US10296673B1

公开(公告)日：2019-05-21

申请号：US14723188

申请日：2015-05-27

Applicant: Xilinx, Inc.

Inventor： Ishita Ghosh ,  Hem C. Neema ,  Jason Villarreal ,  Saikat Bandyopadhyay ,  Kumar Deepak

IPC: G06F17/50

Abstract: For generating code for simulation of a circuit design, a hardware description language (HDL) description and a high-level language (HLL) description of portions of the circuit design are input. The HLL description specifies a first function and the HDL description includes a call to the first function. A wrapper is generated for the first function. The wrapper has an associated stack frame and includes code that stores in the stack frame values of arguments specified by the call to the first function and code that calls the first function. An HLL simulation specification is generated from the HDL description. The HLL simulation specification includes a call to the first HLL wrapper in place of the call to the first function. The HLL simulation specification, the first HLL wrapper, and the HLL description are compiled into executable program code.

公开(公告)号：US10255400B1

公开(公告)日：2019-04-09

申请号：US15473883

申请日：2017-03-30

Applicant: Xilinx, Inc.

Inventor： Jason Villarreal ,  Xiaoyong Liu ,  Kumar Deepak

IPC: G06F17/50

Abstract: Disclosed approaches for configuring a memory include generating by a high-level synthesis (HLS) tool executing on a computer system, a first mapping of elements of a high-level language (HLL) program to elements of a hardware language finite state machine that represents a circuit implementation of the HLL program. The HLS tool further generates a second mapping of lines of the HLL program to states of the hardware language finite state machine and stores the information describing the first mapping and the second mapping in a data structure of a database in the memory.

公开(公告)号：US09977758B1

公开(公告)日：2018-05-22

申请号：US14887080

申请日：2015-10-19

Applicant: Xilinx, Inc.

Inventor： Paul R. Schumacher ,  Kumar Deepak ,  Graham F. Schelle

IPC: G06F13/42 ,  G06F9/445

CPC classification number: G06F13/4221 ,  G06F2212/1016 ,  G06F2212/1024

Abstract: A system may include a first region implemented in programmable circuitry of a programmable integrated circuit. The first region may include predefined interface circuitry configured to communicate with a host processor. The system may include a second region implemented in the programmable circuitry of the programmable integrated circuit. The second region may include a first hardware accelerated kernel of an OpenCL application. The system may include a first monitor circuit implemented within the first region or the second region. The first hardware accelerated kernel and the first monitor circuit may be coupled to the interface circuitry of the first region. The first monitor circuit may be operable responsive to control signals received from the host processor of a platform through the interface circuitry to store operation data for the first region or the first hardware accelerated kernel.

公开(公告)号：US09223910B1

公开(公告)日：2015-12-29

申请号：US14159855

申请日：2014-01-21

Applicant: Xilinx, Inc.

Inventor： Ishita Ghosh ,  Saikat Bandyopadhyay ,  Kumar Deepak ,  Hem C. Neema ,  David K. Liddell

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: A method for compiling an HDL specification for simulation of a circuit design is disclosed. The circuit design is elaborated from the HDL specification and memory locations are allocated for formals and actuals of the elaborated circuit design. For each port having a formal and an actual that are compatible, the allocating of memory locations sets a reference pointer for the formal and a reference pointer for the actual to reference a same one of the memory locations. For each port having a formal and an actual that are incompatible, the allocating of memory locations sets the reference pointer for the formal and the reference pointer for the actual to reference different respective ones of the memory locations. Simulation code modeling the elaborated circuit design is generated that updates a formal and actual of a port that are compatible using a single write operation to the referenced memory location.

Abstract translation: 公开了一种用于编译用于模拟电路设计的HDL规范的方法。 电路设计由HDL规范进行阐述，内存位置分配给精密电路设计的正式和实际。 对于具有兼容的形式和实际的每个端口，存储器位置的分配设置用于形式的参考指针和用于实际引用相同存储器位置的引用指针。 对于具有不兼容的形式和实际的每个端口，存储器位置的分配设置形式的参考指针和用于实际引用的参考指针以引用不同的相应存储器位置。 生成针对详细电路设计的仿真代码建模，其将使用单个写入操作兼容的端口的正式和实际更新到引用的存储器位置。