公开(公告)号：US09147024B1

公开(公告)日：2015-09-29

申请号：US14535258

申请日：2014-11-06

Applicant: Xilinx, Inc.

Inventor： Vinod K. Kathail ,  Hua Sun ,  Sundararajarao Mohan ,  L. James Hwang ,  Yogesh L. Chobe

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5045

Abstract: Hardware and software co-synthesis performance estimation includes, for a design specified in a high level programming language and having a processor executable partition and a partition selected for hardware acceleration, estimating hardware latency for a hardware accelerator implementation of the selected partition, scheduling the selected partition using the hardware latency generating hardware partition latency information, and compiling an instrumented version of the design using a processor. The instrumented and compiled version of the design is executed generating software latency information. A design performance for the design is determined through combining the hardware partition latency information with the software latency information.

Abstract translation: 硬件和软件协同合成性能估计包括对于以高级编程语言指定的设计并具有处理器可执行分区和为硬件加速选择的分区，估计所选分区的硬件加速器实现的硬件延迟，调度所选择的 分区，使用硬件延迟生成硬件分区延迟信息，并使用处理器编译设计版本的设计。 设计的仪器化和编译版本执行生成软件延迟信息。 通过将硬件分区延迟信息与软件延迟信息相结合来确定设计的设计性能。

公开(公告)号：US11645053B2

公开(公告)日：2023-05-09

申请号：US17500509

申请日：2021-10-13

Applicant: Xilinx, Inc.

Inventor： Akella Sastry ,  Vinod K. Kathail ,  L. James Hwang ,  Shail Aditya Gupta ,  Vidhumouli Hunsigida ,  Siddharth Rele

IPC: G06F8/41 ,  H03K19/17724

CPC classification number: G06F8/41 ,  G06F8/447 ,  H03K19/17724

Abstract: Implementing an application within an integrated circuit (IC) having a data processing engine (DPE) array coupled to a Network-on-Chip (NoC) can include determining, using computer hardware, data transfer requirements for a software portion of the application intended to execute on the DPE array by simulating data traffic to the NoC as generated by the software portion, generating, using the computer hardware, a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion. The software portion can be compiled for execution by different ones of a plurality of DPEs of the DPE array based, at least in part, on the NoC routing solution. Configuration data can be generated using the computer hardware. The configuration data, when loaded into the IC, configures the NoC to implement the NoC routing solution.

公开(公告)号：US11188312B2

公开(公告)日：2021-11-30

申请号：US16421444

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Akella Sastry ,  Vinod K. Kathail ,  L. James Hwang ,  Shail Aditya Gupta ,  Vidhumouli Hunsigida ,  Siddharth Rele

IPC: G06F8/41 ,  H03K19/17724

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

公开(公告)号：US20220035607A1

公开(公告)日：2022-02-03

申请号：US17500509

申请日：2021-10-13

Applicant: Xilinx, Inc.

Inventor： Akella Sastry ,  Vinod K. Kathail ,  L. James Hwang ,  Shail Aditya Gupta ,  Vidhumouli Hunsigida ,  Siddharth Rele

IPC: G06F8/41 ,  H03K19/17724

Abstract: Implementing an application within an integrated circuit (IC) having a data processing engine (DPE) array coupled to a Network-on-Chip (NoC) can include determining, using computer hardware, data transfer requirements for a software portion of the application intended to execute on the DPE array by simulating data traffic to the NoC as generated by the software portion, generating, using the computer hardware, a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion. The software portion can be compiled for execution by different ones of a plurality of DPEs of the DPE array based, at least in part, on the NoC routing solution. Configuration data can be generated using the computer hardware. The configuration data, when loaded into the IC, configures the NoC to implement the NoC routing solution.

公开(公告)号：US09880966B1

公开(公告)日：2018-01-30

申请号：US14845127

申请日：2015-09-03

Applicant: Xilinx, Inc.

Inventor： L. James Hwang ,  Vinod K. Kathail ,  Sundararajarao Mohan ,  Jorge E. Carrillo ,  Hua Sun

IPC: G06F13/24 ,  G06F13/40 ,  G06F13/42 ,  G06F3/00

CPC classification number: G06F13/4256 ,  G06F13/24 ,  G06F13/4022

Abstract: Application-specific tailoring and reuse of a platform for a target integrated circuit may include determining, using a processor, a plurality of unused interfaces of the platform and determining, using the processor, connectivity of a circuit block to be coupled to the platform within the target integrated circuit. The method may include coupling, using the processor, the circuit block to the platform using an interface that is compatible with the circuit block and selected from the plurality of unused interfaces of the platform.

公开(公告)号：US09223921B1

公开(公告)日：2015-12-29

申请号：US14540854

申请日：2014-11-13

Applicant: Xilinx, Inc.

Inventor： Jorge E. Carrillo ,  L. James Hwang ,  Hua Sun ,  Sundararajarao Mohan ,  Vinod K. Kathail

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F8/447

Abstract: In an example implementation, a method is provided for compiling an HLL source file. The HLL source file checked for function calls to a set of hardware-accelerated functions having hardware implementations specified in a hardware library. For each HLL function call to a hardware-accelerated function, a circuit design is retrieved from the hardware library. The circuit design specifies a hardware implementation of the hardware-accelerated function. HLL interface code configured to communicate with the hardware implementation of the hardware-accelerated function is also generated. The HLL function call to the hardware-accelerated function in the HLL source file is replaced with the generated interface code. The HLL source file is compiled to generate a program executable on a processor of a programmable IC. Configuration data is generated that implements the retrieved circuit designs on the programmable circuitry of the programmable IC.

Abstract translation: 在一个示例实现中，提供了一种用于编译HLL源文件的方法。 HLL源文件检查了对硬件库中指定的硬件实现的一组硬件加速功能的函数调用。 对于硬件加速功能的每个HLL函数调用，从硬件库检索电路设计。 电路设计规定了硬件加速功能的硬件实现。 HLL接口代码配置为与硬件通信实现硬件加速功能也被生成。 HLL源文件中的硬件加速功能的HLL函数调用将替换为生成的接口代码。 HLL源文件被编译成在可编程IC的处理器上生成可执行的程序。 生成配置数据，其实现在可编程IC的可编程电路上检索的电路设计。

公开(公告)号：US08762916B1

公开(公告)日：2014-06-24

申请号：US13776318

申请日：2013-02-25

Applicant: Xilinx, Inc.

Inventor： Vinod K. Kathail ,  L. James Hwang ,  Sundararajarao Mohan ,  Hua Sun

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5054

Abstract: A method of automatically developing a data transfer network includes determining, using a processor, a plurality of data transfers of a function of a circuit design marked for hardware acceleration within a target integrated circuit. The circuit design is specified in a high level programming language, and at least one other function of the circuit design remains executable by a microprocessor of the target integrated circuit. Each of the plurality of data transfers is characterized. Each of the plurality of data transfers is correlated with resources of the target integrated circuit. A programmatic description of a data transfer network is generated for the circuit design. The data transfer network connects the hardware accelerator and the microprocessor according to the characterizing and the correlating.

Abstract translation: 自动开发数据传输网络的方法包括：使用处理器来确定在目标集成电路内标记为硬件加速的电路设计的功能的多个数据传输。 电路设计以高级编程语言指定，并且电路设计的至少一个其他功能仍然可以由目标集成电路的微处理器执行。 多个数据传输中的每一个都被表征。 多个数据传输中的每一个与目标集成电路的资源相关。 为电路设计生成数据传输网络的编程描述。 数据传输网络根据特征和相关性连接硬件加速器和微处理器。

公开(公告)号：US10977018B1

公开(公告)日：2021-04-13

申请号：US16704890

申请日：2019-12-05

Applicant: Xilinx, Inc.

Inventor： L. James Hwang ,  Michael Gill ,  Tom Shui ,  Jorge E. Carrillo ,  Alfred Huang ,  Sudipto Chakraborty

IPC: G06F9/44 ,  G06F8/41 ,  G06F8/30

Abstract: Implementing an application within a heterogeneous device can include receiving an application specifying a plurality of hardware accelerators and having a plurality of sections corresponding to different subsystems of the heterogeneous device, wherein the plurality of sections are specified using different programming models. Compiling each section based on the programming model of the section and the subsystem of the heterogeneous device corresponding to the section into an accelerator representation. Linking the accelerator representations based on a platform of the heterogeneous device, generating a hardware implementation of the application for the heterogeneous device based on the linked accelerator implementations, and automatically generating program code configured to control one or more of the plurality of hardware accelerators of the hardware implementation.

公开(公告)号：US20200371759A1

公开(公告)日：2020-11-26

申请号：US16421444

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Akella Sastry ,  Vinod K. Kathail ,  L. James Hwang ,  Shail Aditya Gupta ,  Vidhumouli Hunsigida ,  Siddarth Rele

IPC: G06F8/41 ,  H03K19/177

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

公开(公告)号：US09805152B1

公开(公告)日：2017-10-31

申请号：US15046147

申请日：2016-02-17

Applicant: Xilinx, Inc.

Inventor： Jorge E. Carrillo ,  Vinod K. Kathail ,  L. James Hwang ,  Sundararajarao Mohan ,  Hua Sun

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: In an example implementation, a method is provided for compiling an HLL source file including function calls to one or more hardware accelerated functions. Function calls in the HLL source file to hardware accelerated functions are identified and grouped into a plurality of subsets for exclusive implementation in programmable logic resources. Sets of configuration data are generated for configuration of the programmable logic resources to implement hardware accelerated functions for the respective subsets of function calls. An interface manager is generated and the identified function calls are replaced with interface code configured to communicate with the interface manager. The interface manager manages configuration of the programmable logic resources to switch between the sets of configuration data to implement hardware accelerated functions for different ones of the subsets.