公开(公告)号：US20240330558A1

公开(公告)日：2024-10-03

申请号：US18193197

申请日：2023-03-30

Applicant: Xilinx, Inc.

Inventor： Jichun Wang ,  Wuxi Li ,  Chun Zhang ,  Paul Kundarewich ,  John Blaine

IPC: G06F30/392

CPC classification number: G06F30/392

Abstract: Implementing circuit designs in integrated circuit devices includes determining, using computer hardware, regular control sets, super control sets, and mega control sets for a circuit design. Control set optimization is performed on the circuit design. Performing control set optimization includes performing a clock-enable-only control set reduction for each super control set. Performing control set optimization includes performing a set/reset control set reduction and a clock-enable control set reduction for each mega control set. The circuit design is selectively modified by committing changes determined from the control set reductions to the circuit design on a per control set basis based on an improvement of a cost metric for each control set.

公开(公告)号：US12019964B1

公开(公告)日：2024-06-25

申请号：US17376892

申请日：2021-07-15

Applicant: Xilinx, Inc.

Inventor： Karthic P ,  Paul Kundarewich ,  Satish Sivaswamy ,  Meghraj Kalase ,  Vishal Tripathi ,  Srinivasan Dasasathyan ,  Mehrdad Eslami Dehkordi ,  Xiaojian Yang ,  Amish Pandya

IPC: G06F30/337 ,  G06F30/392 ,  G06N20/00

CPC classification number: G06F30/337 ,  G06F30/392 ,  G06N20/00

Abstract: Methods and systems for selecting between single-process and multi-process implementation flows involve identifying features of a circuit design by a design tool. A classification model is applied to the features. The classification model indicates whether an implementation flow on the circuit design is likely to have a runtime within a first range of runtimes or a runtime within a second range of runtimes. The implementation flow is executed by the design tool in a single process in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the first range of runtimes. The implementation flow is executed by the design tool in a plurality of processes in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the second range of runtimes.