公开(公告)号：US11824830B2

公开(公告)日：2023-11-21

申请号：US17246310

申请日：2021-04-30

Applicant: Xilinx, Inc.

Inventor： Steven Leslie Pope ,  Neil Turton ,  David James Riddoch ,  Dmitri Kitariev ,  Ripduman Sohan ,  Derek Edward Roberts

IPC: H04L29/06 ,  H04L9/40

CPC classification number: H04L63/0227 ,  H04L63/029

Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.

公开(公告)号：US11689648B2

公开(公告)日：2023-06-27

申请号：US17199202

申请日：2021-03-11

Applicant: XILINX, INC.

Inventor： Steven Leslie Pope ,  Derek Edward Roberts ,  Dmitri Kitariev ,  Neil Duncan Turton ,  David James Riddoch ,  Ripduman Sohan

IPC: G06F15/173 ,  H04L69/22 ,  H04L47/34 ,  H04L67/1097 ,  H04L69/326

CPC classification number: H04L69/22 ,  H04L47/34 ,  H04L67/1097 ,  H04L69/326

Abstract: A network interface device comprises an input configured to receive a storage response comprising a plurality of packets of data, one or more packets comprising a header part and data to be stored, the header part comprising a transport protocol header and a data storage application header. A first packet processor is configured to receive two or more of said plurality of packets and perform transport protocol processing of the received packets to provide transport protocol processed packets A second packet processor configured to receive the transport protocol processed packets from the first packet processor, to write the data to be stored of the received packets to memory and to provide the data storage application header and a pointer to a location in the memory to which the data has been written.

公开(公告)号：US20210258284A1

公开(公告)日：2021-08-19

申请号：US17246310

申请日：2021-04-30

Applicant: Xilinx, Inc.

Inventor： Steven Leslie Pope ,  Neil Turton ,  David James Riddoch ,  Dmitri Kitariev ,  Ripduman Sohan ,  Derek Edward Roberts

IPC: H04L29/06

Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.

公开(公告)号：US11012411B2

公开(公告)日：2021-05-18

申请号：US16180883

申请日：2018-11-05

Applicant: Xilinx, Inc.

Inventor： Steven Leslie Pope ,  Neil Turton ,  David James Riddoch ,  Dmitri Kitariev ,  Ripduman Sohan ,  Derek Edward Roberts

IPC: H04L29/06

Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.

公开(公告)号：US20250147799A1

公开(公告)日：2025-05-08

申请号：US18501868

申请日：2023-11-03

Applicant: Xilinx, Inc.

Inventor： Thomas Calvert ,  Ripduman Sohan ,  Dmitri Kitariev ,  Kimon Karras ,  Stephan Diestelhorst ,  Neil Turton ,  David Riddoch ,  Derek Roberts ,  Kieran Mansley ,  Steven Pope

IPC: G06F9/48

Abstract: A computer-implemented method for task management can include managing performance of a task on a message by a plurality of circuits. In some aspects, the task can comprise a sequence of processings to be performed on the message and each circuit of the plurality of circuits performing a processing of the sequence of processings. In some aspects, the method can include routing, based on the sequence, a first information regarding the task to a first circuit of the plurality of circuits to perform a first processing of the sequence of processings on the message; receiving, from the first circuit, an output of the first processing; and routing, based on the sequence of processings identified for the task, a second information regarding the task to a second circuit of the plurality of circuits to perform a second processing that follows the first processing in the sequence of processings.

公开(公告)号：US11960596B2

公开(公告)日：2024-04-16

申请号：US17199200

申请日：2021-03-11

Applicant: XILINX, INC.

Inventor： Steven Leslie Pope ,  Derek Edward Roberts ,  Dmitri Kitariev ,  Neil Duncan Turton ,  David James Riddoch ,  Ripduman Sohan

IPC: G06F21/53 ,  G06F21/57 ,  H04L9/40

CPC classification number: G06F21/53 ,  G06F21/57 ,  H04L63/0218

Abstract: A network interface device comprises a first area of trust comprising a first part of the network interface device, the first part comprising one or more first kernels. A second area of trust comprising a second part of the network interface device different to said first part is provided, the second part comprising one or more second kernels. A communication link is provided between the first area of trust and the second area of trust. At least one of the first and second areas of trust is provided with isolation circuitry configured to control which data which is passed to the other of the first and second areas via the communication link.

公开(公告)号：US11966351B2

公开(公告)日：2024-04-23

申请号：US17199197

申请日：2021-03-11

Applicant: XILINX, INC.

Inventor： Steven Leslie Pope ,  Derek Edward Roberts ,  Dmitri Kitariev ,  Neil Duncan Turton ,  David James Riddoch ,  Ripduman Sohan

IPC: G06F9/445 ,  G06F9/48 ,  G06F11/36 ,  G06F13/40

CPC classification number: G06F13/4068 ,  G06F9/4881

Abstract: A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first upstream data path entity and from a first data processing entity implemented in programmable circuitry via a data ingress interface of the first hub. The first data processing engine is configured to receive data from the first hub, process the received data and output the processed data to the second hub arranged downstream of first data processing engine.

公开(公告)号：US11726928B2

公开(公告)日：2023-08-15

申请号：US17357083

申请日：2021-06-24

Applicant: XILINX, INC.

Inventor： Steven Leslie Pope ,  Derek Edward Roberts ,  Dmitri Kitariev ,  Neil Duncan Turton ,  David James Riddoch ,  Ripduman Sohan

IPC: G06F13/16 ,  G06F13/28 ,  G11C7/10

CPC classification number: G06F13/1621 ,  G06F13/1642 ,  G06F13/1678 ,  G06F13/287 ,  G11C7/1069 ,  G11C7/1096

Abstract: A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.

公开(公告)号：US11082364B2

公开(公告)日：2021-08-03

申请号：US16395027

申请日：2019-04-25

Applicant: Xilinx, Inc.

Inventor： Steven Leslie Pope ,  Neil Turton ,  David James Riddoch ,  Dmitri Kitariev ,  Ripduman Sohan ,  Derek Edward Roberts

IPC: H04L12/947 ,  H04L29/06 ,  G06F9/24 ,  G06F9/28 ,  G06F9/30 ,  G06F8/41 ,  H03K19/177

Abstract: A method comprises receiving at a compiler a bit file description and a program, said bit file description comprising a description of routing of a part of a circuit. The method comprises compiling the program using said bit file description to output a bit file for said program.