公开(公告)号：US20160259756A1

公开(公告)日：2016-09-08

申请号：US14638692

申请日：2015-03-04

Applicant: XILINX, INC.

Inventor： Sagheer Ahmad ,  Soren Brinkmann

IPC: G06F15/167 ,  G06F13/16 ,  G06F13/42 ,  G06F12/14 ,  G06F13/24

CPC classification number: G06F15/167 ,  G06F12/1425 ,  G06F13/1673 ,  G06F13/24 ,  G06F13/4221 ,  G06F15/17 ,  G06F15/17337 ,  G06F2212/1052 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various example implementations are directed to circuits and methods for communicating between disparate processor circuits. According to an example implementation, a circuit arrangement includes a plurality of processor circuits and an inter-processor communication circuit. The inter-processor communication circuit is configured to provide, for each pair of the processor circuits, a respective communication channel between the pair of processor circuits. The inter-processor communication circuit includes a plurality of buffers including a respective first buffer and a respective second buffer for each communication channel. An access control circuit included in the inter-processor communication circuit is configured to restrict write access to the respective first buffer to the first processor circuit and restrict write access to the respective second buffer to the second processor circuit.

Abstract translation: 各种示例性实现涉及用于在不同处理器电路之间进行通信的电路和方法。 根据示例实现，电路装置包括多个处理器电路和处理器间通信电路。 处理器间通信电路被配置为为每对处理器电路提供一对处理器电路之间的相应通信信道。 处理器间通信电路包括多个缓冲器，包括用于每个通信信道的相应的第一缓冲器和相应的第二缓冲器。 包括在处理器间通信电路中的访问控制电路被配置为限制对第一处理器电路的相应的第一缓冲区的写入访问，并限制对第二处理器电路的各个第二缓冲区的写入访问。

公开(公告)号：US09696789B2

公开(公告)日：2017-07-04

申请号：US14462492

申请日：2014-08-18

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Ahmad R. Ansari ,  Soren Brinkmann

IPC: G06F1/32 ,  G06F13/24

CPC classification number: G06F1/3287 ,  G06F1/3215 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/24 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: An apparatus is disclosed that includes a processing sub-system having a plurality of processor circuits and an interrupt control circuit. The interrupt control circuit is configured to, in response to a peripheral interrupt, initiate performance of a task indicated by the peripheral interrupt by at least one of the plurality of processor circuits. The processing sub-system is configured to generate a power-down control signal in response to suspension of the plurality of processor circuits. A power management circuit disables power to the processing sub-system, including the interrupt control circuit, in response to the power-down control signal. The power management circuit enables power to the processing sub-system in response to a power-up control signal. The apparatus also includes a proxy interrupt control circuit configured to generate the power-up control signal in response to receiving a peripheral interrupt and power to the processing sub-system being disabled.

公开(公告)号：US10037301B2

公开(公告)日：2018-07-31

申请号：US14638692

申请日：2015-03-04

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Soren Brinkmann

IPC: G06F15/17 ,  G06F15/167 ,  G06F12/14 ,  G06F13/24 ,  G06F13/42 ,  G06F13/16 ,  G06F15/173

CPC classification number: G06F15/167 ,  G06F12/1425 ,  G06F13/1673 ,  G06F13/24 ,  G06F13/4221 ,  G06F15/17 ,  G06F15/17337 ,  G06F2212/1052 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various example implementations are directed to circuits and methods for communicating between disparate processor circuits. According to an example implementation, a circuit arrangement includes a plurality of processor circuits and an inter-processor communication circuit. The inter-processor communication circuit is configured to provide, for each pair of the processor circuits, a respective communication channel between the pair of processor circuits. The inter-processor communication circuit includes a plurality of buffers including a respective first buffer and a respective second buffer for each communication channel. An access control circuit included in the inter-processor communication circuit is configured to restrict write access to the respective first buffer to the first processor circuit and restrict write access to the respective second buffer to the second processor circuit.

公开(公告)号：US20160048193A1

公开(公告)日：2016-02-18

申请号：US14462492

申请日：2014-08-18

Applicant: XILINX, INC.

Inventor： Sagheer Ahmad ,  Ahmad R. Ansari ,  Soren Brinkmann

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3215 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/24 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: An apparatus is disclosed that includes a processing sub-system having a plurality of processor circuits and an interrupt control circuit. The interrupt control circuit is configured to, in response to a peripheral interrupt, initiate performance of a task indicated by the peripheral interrupt by at least one of the plurality of processor circuits. The processing sub-system is configured to generate a power-down control signal in response to suspension of the plurality of processor circuits. A power management circuit disables power to the processing sub-system, including the interrupt control circuit, in response to the power-down control signal. The power management circuit enables power to the processing sub-system in response to a power-up control signal. The apparatus also includes a proxy interrupt control circuit configured to generate the power-up control signal in response to receiving a peripheral interrupt and power to the processing sub-system being disabled.

Abstract translation: 公开了一种包括具有多个处理器电路和中断控制电路的处理子系统的装置。 中断控制电路被配置为响应于外围中断，由多个处理器电路中的至少一个启动由外设中断指示的任务的执行。 处理子系统被配置为响应于多个处理器电路的暂停而产生掉电控制信号。 功率管理电路响应于掉电控制信号而禁止包括中断控制电路在内的处理子系统的电力。 电源管理电路响应于上电控制信号使处理子系统能够供电。 该设备还包括代理中断控制电路，其配置为响应于接收到外围中断而产生加电控制信号，并且对被禁用的处理子系统的电力。