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    User-configurable error handling
    3.
    发明授权
    User-configurable error handling 有权
    用户可配置的错误处理

    公开(公告)号：US09495239B1

    公开(公告)日：2016-11-15

    申请号：US14466845

    申请日：2014-08-22

    Applicant: Xilinx, Inc.

    Inventor： Sagheer Ahmad ,  Bradley L. Taylor ,  Ahmad R. Ansari ,  Tomai Knopp

    IPC: G06F11/07 ,  G06F11/14

    CPC classification number: G06F11/0793 ,  G06F11/0706 ,  G06F11/0772 ,  G06F11/142 ,  G06F11/1441

    Abstract: A method for operating a programmable IC is disclosed. A set of circuits specified by a set of configuration data is operated in a set of programmable resources. In response to one of a set of status signals indicating an error, a value indicative of an error is stored in a respective one of a plurality of error status registers. The values stored in the plurality of error status registers are provided to an error handling circuit included in the set of circuits specified by the set of configuration data and operated in the programmable resources. At least one error handling process is performed by the error handling circuit as a function of values stored in the plurality of error status registers.

    Abstract translation: 公开了一种用于操作可编程IC的方法。 由一组配置数据指定的一组电路在一组可编程资源中操作。 响应于指示错误的一组状态信号中的一个，指示错误的值被存储在多个错误状态寄存器中的相应一个中。 存储在多个错误状态寄存器中的值被提供给由该组配置数据指定并在可编程资源中操作的电路集合中包括的错误处理电路。 由错误处理电路执行至少一个错误处理过程作为存储在多个错误状态寄存器中的值的函数。

    NoC routing in a multi-chip device
    4.
    发明授权
    NoC routing in a multi-chip device 有权

    公开(公告)号：US12235782B2

    公开(公告)日：2025-02-25

    申请号：US18086531

    申请日：2022-12-21

    Applicant: XILINX, INC.

    Inventor： Aman Gupta ,  Krishnan Srinivasan ,  Ahmad R. Ansari ,  Sagheer Ahmad

    IPC: G06F13/40 ,  G06F12/1009

    Abstract: Embodiments herein describe a multi-chip device that includes multiple ICs with interconnected NoCs. Embodiments herein provided address translation circuitry in the ICs. The address translation circuitry establish a hierarchy where traffic originating for a first IC that is intended for a destination on a second IC is first routed to the address translation circuitry on the second IC which then performs an address translation and inserts the traffic back on the NoC in the second IC but with a destination ID corresponding to the destination. In this manner, the IC can have additional address apertures only to route traffic to the address translation circuitry of the other ICs rather than having address apertures for every destination in the other ICs.

    Debug controller circuit
    5.
    发明授权
    Debug controller circuit 有权

    公开(公告)号：US10789153B2

    公开(公告)日：2020-09-29

    申请号：US15944137

    申请日：2018-04-03

    Applicant: Xilinx, Inc.

    Inventor： Ahmad R. Ansari ,  Felix Burton ,  Ming-dong Chen

    IPC: G06F11/00 ,  G06F11/36 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/267 ,  G06F11/273 ,  G06F30/34

    Abstract: A circuit arrangement includes one or more input buffers disposed on a system-on-chip (SoC) and configured to receive and store streaming debug packets. One or more response buffers are also disposed on the SoC. A transaction control circuit is disposed on the SoC and is configured to process each debug packet in the one or more input buffers. The processing includes decoding an operation code in the debug packet, and determining from an address in the debug packet, an interface circuit of multiple interface circuits to access a storage circuit in a subsystem of multiple sub-systems on the SoC. The processing further includes issuing a request via the interface circuit to access the storage circuit according to the operation code, and storing responses and data received from the interface circuits in the one or more response buffers.

    Input/output path testing and characterization using scan chains
    6.
    发明授权
    Input/output path testing and characterization using scan chains 有权

    公开(公告)号：US10067189B1

    公开(公告)日：2018-09-04

    申请号：US15464217

    申请日：2017-03-20

    Applicant: Xilinx, Inc.

    Inventor： Banadappa V. Shivaray ,  Ahmad R. Ansari ,  Sanjeeva R. Duggampudi ,  Pramod Surathkal ,  Ushasri Merugu ,  Bommana S. Rao ,  Sowmya Sheela Thati ,  Shashidhar S. Krishnamurthy

    IPC: G01R31/3185 ,  G01R31/3177 ,  G01R31/317

    Abstract: Disclosed circuitry includes input-output pads, receive flip-flops, and transmit flip-flops coupled to the input-output pads. Data path control circuitry is coupled to data path control flip-flops, the receive flip-flops and the transmit flip-flops. The data path control circuitry is configured to selectably couple the receive flip-flops and the transmit flip-flops to the input-output pads in response to states of the data path control flip-flops. Clock control circuitry is coupled to clock control flip-flops, the receive flip-flops and the transmit flip-flops. The clock control circuitry is configured to selectably apply one of multiple clock signals to the receive flip-flops and the transmit flip-flops in response to states of the clock control flip-flops. A first scan chain is coupled to the clock control flip-flops and the data path control flip-flops. A second scan chain is coupled to the receive flip-flops and the transmit flip-flops.

    Mechanism for inter-processor interrupts in a heterogeneous multiprocessor system
    7.
    发明授权
    Mechanism for inter-processor interrupts in a heterogeneous multiprocessor system 有权

    公开(公告)号：US09665509B2

    公开(公告)日：2017-05-30

    申请号：US14464654

    申请日：2014-08-20

    Applicant: Xilinx, Inc.

    Inventor： Ahmad R. Ansari ,  Felix Burton

    IPC: G06F13/24 ,  G06F9/48

    CPC classification number: G06F13/24 ,  G06F9/4812

    Abstract: Apparatus and methods for handling inter-processor interrupts (IPIs) in a heterogeneous multiprocessor system are provided. The scalable IPI mechanism provided herein entails minimal logic and can be used for heterogeneous inter-processor communication, such as between application processors, real-time processors, and FPGA accelerators. This mechanism is also low cost, in terms of both logic area and programmable complexity. One example system generally includes a first processor, a second processor being of a different processor type than the first processor, and an IPI circuit. The IPI circuit typically includes a first register associated with the first processor, wherein a first bit in the first register indicates whether the first processor has requested to interrupt the second processor; and a second register associated with the second processor, wherein a second bit in the second register indicates whether the second processor has requested to interrupt the first processor.

    Synchronization of system resources in a multi-socket data processing system
    8.
    发明授权
    Synchronization of system resources in a multi-socket data processing system 有权

    公开(公告)号：US12223355B2

    公开(公告)日：2025-02-11

    申请号：US17455074

    申请日：2021-11-16

    Applicant: Xilinx, Inc.

    Inventor： Karthik Shankar ,  Jaideep Dastidar ,  Ahmad R. Ansari ,  Sagheer Ahmad

    IPC: G06F9/44 ,  G06F9/50

    Abstract: Synchronizing system resources of a multi-socket data processing system can include providing, from a primary System-on-Chip (SOC), a trigger event to a global synchronization circuit. The primary SOC is one of a plurality of SOCS and the trigger event is provided over a first sideband channel. In response to the trigger event, the global synchronization circuit is capable of broadcasting a synchronization event to the plurality of SOCS over a second sideband channel. In response to the synchronization event, the system resource of each SOC of the plurality of SOCS is programmed with a common value. The programming synchronizes the system resources of the plurality of SOCS.

    Register integrity check in configurable devices
    9.
    发明授权
    Register integrity check in configurable devices 有权

    公开(公告)号：US12124323B2

    公开(公告)日：2024-10-22

    申请号：US17883379

    申请日：2022-08-08

    Applicant: XILINX, INC.

    Inventor： Ahmad R. Ansari ,  David P. Schultz ,  Felix Burton ,  Jeffrey Cuppett

    IPC: G06F11/07 ,  G06F9/30

    CPC classification number: G06F11/0763 ,  G06F9/30101 ,  G06F11/0772

    Abstract: Embodiments herein describe integrity check techniques that are efficient and flexible by using local registers in a segment to store check values which can be used to detect errors in the local configuration data in the same segment. In addition to containing local registers storing the check values, each segment can include a mask register indicated which of the configuration registers should be checked and which can be ignored. Further, the segments can include a next segment register indicating the next segment the check engine should evaluate for errors.

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