公开(公告)号：US11960596B2

公开(公告)日：2024-04-16

申请号：US17199200

申请日：2021-03-11

Applicant: XILINX, INC.

Inventor： Steven Leslie Pope ,  Derek Edward Roberts ,  Dmitri Kitariev ,  Neil Duncan Turton ,  David James Riddoch ,  Ripduman Sohan

IPC: G06F21/53 ,  G06F21/57 ,  H04L9/40

CPC classification number: G06F21/53 ,  G06F21/57 ,  H04L63/0218

Abstract: A network interface device comprises a first area of trust comprising a first part of the network interface device, the first part comprising one or more first kernels. A second area of trust comprising a second part of the network interface device different to said first part is provided, the second part comprising one or more second kernels. A communication link is provided between the first area of trust and the second area of trust. At least one of the first and second areas of trust is provided with isolation circuitry configured to control which data which is passed to the other of the first and second areas via the communication link.

公开(公告)号：US20220086042A1

公开(公告)日：2022-03-17

申请号：US17534413

申请日：2021-11-23

Applicant: Xilinx, Inc.

Inventor： Steven Leslie Pope ,  David James Riddoch

IPC: H04L12/24 ,  H04W88/18 ,  H04L12/801

Abstract: A network interface device comprises a plurality of components configured to process a flow of data one after another. A control component is configured to provide one or more control messages in said flow, said one or more control message being provided to said plurality of components one after another such that a configuration of one or more of said components is changed.

公开(公告)号：US11570045B2

公开(公告)日：2023-01-31

申请号：US16146128

申请日：2018-09-28

Applicant: Xilinx, Inc.

Inventor： Steven Leslie Pope ,  David James Riddoch

IPC: H04L12/24 ,  H04W88/18 ,  H04L12/801 ,  H04W80/02 ,  H04L41/0813 ,  H04L47/10

Abstract: A network interface device comprises a plurality of components configured to process a flow of data one after another. A control component is configured to provide one or more control messages in said flow, said one or more control message being provided to said plurality of components one after another such that a configuration of one or more of said components is changed.

公开(公告)号：US11245580B2

公开(公告)日：2022-02-08

申请号：US16146128

申请日：2018-09-28

Applicant: Xilinx, Inc.

Inventor： Steven Leslie Pope ,  David James Riddoch

IPC: H04L12/24 ,  H04W88/18 ,  H04L12/801 ,  H04W80/02

Abstract: A network interface device comprises a plurality of components configured to process a flow of data one after another. A control component is configured to provide one or more control messages in said flow, said one or more control message being provided to said plurality of components one after another such that a configuration of one or more of said components is changed.

公开(公告)号：US20210026689A1

公开(公告)日：2021-01-28

申请号：US17069642

申请日：2020-10-13

Applicant: Xilinx, Inc.

Inventor： Steven Leslie Pope ,  David James Riddoch

IPC: G06F9/48 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0842

Abstract: A network interface device has an input configured to receive data from a network. The data is for one of a plurality of different applications. The network interface device also has at least one processor configured to determine which of a plurality of available different caches in a host system the data is to be injected by accessing to a receive queue comprising at least one descriptor indicating a cache location in one of said plurality of caches to which data is to be injected, wherein said at least one descriptor, which indicates the cache location, has an effect on subsequent descriptors of said receive queue until a next descriptor indicates another cache location. The at least one processor is also configured to cause the data to be injected to the cache location in the host system.

公开(公告)号：US11995021B2

公开(公告)日：2024-05-28

申请号：US17574342

申请日：2022-01-12

Applicant: XILINX, INC.

Inventor： Jaideep Dastidar ,  David James Riddoch ,  Steven Leslie Pope

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4265 ,  G06F13/1684

Abstract: Embodiments herein describe end-to-end bindings to create zones that extend between different components in a SoC, such as an I/O gateway, a processor subsystem, a NoC, storage and data accelerators, programmable logic, etc. Each zone can be assigned to a different domain that is controlled by a tenant such as an external host, or software executing on that host. Embodiments herein create end-to-end bindings between acceleration engines, I/O gateways, and embedded cores in SoCs. Instead of these components being treated as disparate monolithic components, the bindings divide up the hardware and memory resources across components that make up the SoC, into different zones. Those zones in turn can have unique bindings to multiple tenants. The bindings can be configured in bridges between components to divide resources into the zones to enable tenants of those zones to have dedicated available resources that are secure from the other tenants.

公开(公告)号：US11983133B2

公开(公告)日：2024-05-14

申请号：US17892949

申请日：2022-08-22

Applicant: XILINX, INC.

Inventor： Jaideep Dastidar ,  David James Riddoch ,  Steven Leslie Pope

IPC: G06F13/40 ,  G06F13/28

CPC classification number: G06F13/4027 ,  G06F13/28

Abstract: An integrated circuit device includes multiple heterogeneous functional circuit blocks and interface circuitry that permits the heterogeneous functional circuit blocks to exchange data with one another using communication protocols of the respective heterogeneous functional circuit blocks. The IC device includes fixed-function circuitry, user-configurable circuitry (e.g., programmable logic), and/or embedded processors/cores. A functional circuit block may be configured in fixed-function circuitry or in the user-configurable circuitry (i.e., as a plug-in). The interface circuitry includes a network-on-a-chip (NoC), an adaptor configured in the user-configurable circuitry, and/or memory. The memory may be accessible to the functional circuit blocks through an adaptor configured the user-configurable circuitry and/or through the NoC. The IC device may be configured as a SmartNIC, DPU, or other type of system-on-a-chip (SoC).

公开(公告)号：US11924032B2

公开(公告)日：2024-03-05

申请号：US17534413

申请日：2021-11-23

Applicant: Xilinx, Inc.

Inventor： Steven Leslie Pope ,  David James Riddoch

IPC: H04L41/0813 ,  H04L47/10 ,  H04W80/02 ,  H04W88/18

CPC classification number: H04L41/0813 ,  H04L47/10 ,  H04W88/184 ,  H04W80/02

Abstract: A network interface device comprises a plurality of components configured to process a flow of data one after another. A control component is configured to provide one or more control messages in said flow, said one or more control message being provided to said plurality of components one after another such that a configuration of one or more of said components is changed.

公开(公告)号：US11429438B2

公开(公告)日：2022-08-30

申请号：US17069642

申请日：2020-10-13

Applicant: Xilinx, Inc.

Inventor： Steven Leslie Pope ,  David James Riddoch

IPC: G06F15/16 ,  G06F9/48 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0842

Abstract: A network interface device has an input configured to receive data from a network. The data is for one of a plurality of different applications. The network interface device also has at least one processor configured to determine which of a plurality of available different caches in a host system the data is to be injected by accessing to a receive queue comprising at least one descriptor indicating a cache location in one of said plurality of caches to which data is to be injected, wherein said at least one descriptor, which indicates the cache location, has an effect on subsequent descriptors of said receive queue until a next descriptor indicates another cache location. The at least one processor is also configured to cause the data to be injected to the cache location in the host system.

公开(公告)号：US20210258284A1

公开(公告)日：2021-08-19

申请号：US17246310

申请日：2021-04-30

Applicant: Xilinx, Inc.

Inventor： Steven Leslie Pope ,  Neil Turton ,  David James Riddoch ,  Dmitri Kitariev ,  Ripduman Sohan ,  Derek Edward Roberts

IPC: H04L29/06

Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.